AC phase shift using FPGA from input signal

[queenlooners]

Hi all,

I want to read in an AC signal on one of my FPGA AI channels and then output, on an AO channel, another AC signal that is phase shifted a set amount from the AI signal (in degrees).  I am using a NI PXI-7852R FPGA card.  I know there is a way, but I have yet to successfully find a solution.  Please note, you cannot use the DDS waveform generation since I want to feed in an unknown signal as the reference.  I like the idea of how DDS does the shifting but I guess my main issue is the data acquisition portion, before the signal is processed. I believe you could find the peaks of the input signal and then try to make your output signal based on the input peaks…would you recommend FIFO? Or can you do this with just an AI? Looking for ideas please.  Signal frequency is from 400 Hz to 10 KHz.

Thanks!

[Rairiki]

Hi queenlooners

I did some research about your issue and I found this link showing an example of creating a delay between AI and AO. He is using a FIFO

So I thinked that might help you.

https://decibel.ni.com/content/docs/DOC-17954

[queenlooners]

Thanks Rairiki, but that is still not exactly what I am looking for.  Still a good example but I would need something that would allow for "free" shifting between my AC signals.  I want to be able to fully shift my AC signal being input on my AI0 channel a range from 0-360 degrees at any time and output the shifted signal on AO0 channel.  This example does show how to use the FIFO to at least store some segments of the AI0 and how to maybe modify them before outputting on the AO0 but there is still a bit to develop...back to drawing board.

Thanks for responding!

~queenlooners

[Intaris]

What is the frequency of your signal?  How do you want to implement changes in phase shift? Instantaneously, gradual?

[queenlooners]

Want to have full control of the frequency and make it instantaneously adjustable (as a real function generator with a ref input signal).

Would like to have 0 to 100K Hz but for my current project I am working on I would like to mainly run around 6K Hz.

Thanks for any feedback or thoughts. 

[Intaris]

0 kHz is not doable.

What is the input rate of your signal you want to delay? 1MHz?  In order to delay this by 180° at 1Hz you need a FIFO of length at least 512k elements.  That'll pretty much fill your FPGA I think unless you move to RAM.

To be honest, it sounds like you need a PLL and not a variable shift of an input signal.  Are you familiar with PLLs?

[Drew116143]

Hey Intaris, 

I wanted to follow up on this post with a similar question. 

I am taking pressure data as an input (nearly sinusoidal), and would like to output a signal that is phase shifted. Right now, I am using a PLL to "lock on to that signal", but am unsure how to implement a "time delay" that would appear as a phase shift between the signals. Putting a "wait" function or any other similar one seems like a non-starter since this will just affect the loop timing. Do you have any recommendations of how to control the phase shift of the signal output from my PLL?

Best,

Drew