A method to view implementation

[abadobid]

Is there any way to actually view the final design that is generated by LabView FPGA?

Something like a netlist or "schematic" view. 

We have some external IP that we are instantiating in a socketed CLIP.  This IP is basically just the xilinx ISERDES2 primatives and some associtated BUFR, BUFG, and IO buffers.  Is there a way to "view" how this external IP ends up being implemented in LabView FPGA?  I am seeing some warnings in the xilinx log that leaves me wondering if the IP is really implemented as I think.

Thanks

[David-A]

LabVIEW FPGA does not expose the underlying design that gets passed to the Xilinx compiler. However you may find the white paper Generating and Debugging Constraints for High Speed Serial Instruments useful. Though some of the information provided in the document is specific to the open fpga high speed serial instruments, much of the information is generally applicable to any open FPGA device that requires a socketed CLIP.

[abadobid]

Thanks David.  That link is helpful.

[abadobid]

I'm not having much luck trying to write constraints for my sbRIO9651 based design.

Working through the linked document is helpful, but I can't seem to get the right path hierarchy.  To cut things down to the minimum, I even just tried to define a clock based on one of the inputs instead of drilling down into my IP.  In each case I just recieve the warning in the Xilinx log that the pin cannot be found.  Some of the conventions I tried:

create_clock -period 4.000 -name clk_in_p -waveform {0.000 2.000} [get_pins {aDio[61]}]

create_clock -period 4.000 -name clk_in_p -waveform {0.000 2.000} [get_pins {%ClipInstancePath%/aDio[61]}]

create_clock -period 4.000 -name clk_in_p -waveform {0.000 2.000} [get_pins {%ClipInstancePath%/serdes_I_clk_p}]

If I use get_ports instead

create_clock -period 4.000 -name clk_in_p -waveform {0.000 2.000} [get_ports {aDio[61]}]

Then I get a LabView during compilation:

From within Vivado I can define the constraints.  I am just having problems figuring out the path to use when using the IP in a CLIP.