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The NI Idea Exchange is a product feedback forum where NI R&D and users work together to submit ideas, collaborate on their development, and vote for the ones they like best. View all of the NI Idea Exchanges to post an idea or add your opinion on an existing one today!
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Alex.T

For Loop within Single Cyle Timed Loop

Status: New
by Active Participant Alex.T on ‎05-10-2013 02:56 PM

In current versions of LabVIEW FPGA, placing a For Loop inside an SCTL will result in code that cannot be compiled; this is because conventially For Loops work iteratively and therefore require multiple clock signals to drive each new iteration.

 

However, I think a logical implementation of a For Loop within an SCTL would be the generation of multiple parallelised instances of whatever code is inside the For Loop. This would greatly improve readability and flexibility by avoiding the user having to manually create multiple separate instances of the same critical code on the Block Diagram.

 

This would require the For Loop to execute a known maximum number of times.

 

SCTLs.png

 

 

Piotr_Kruczkowski

Lets enqueue creating intermediate files

Status: New
by Active Participant Piotr_Kruczkowski on ‎10-18-2013 02:40 AM

Hi, since there an be a queue for compiling FPGA code, it seems natural to me to also be able to make a queue for generating intermediate files.

 

I'm working with 10 build specs. for compilation per project and generating intermediate files for my design takes aprox. 3-4 minutes. This means that I need to sit by my computer for half an hour just waiting and clicking build on every build specification. Sometimes I work with FPGA VI which need to build intermediate files for something like 7-10 minutes, so this is a pain.

 

It would be great if there was a way of just highlighting all build specifications for compilation with shift and just creating the intermediate files for them automatically one by one.

 

Can this be done?

adalyn

Parallel loop support

Status: New
by Member adalyn on ‎07-25-2010 09:42 PM

Parallel loops are supported by LabVIEW but not LabVIEW FPGA, this requires us to copy/paste the same blocks multiple times to make them run in parallel.  I would like to see the ability to use parallel loops on FPGA targets as FPGAs are very well suited to this style of programming and the current copy/paste parallelism hinders this.

 

 

MrQuestion

memory map

Status: New
by Member MrQuestion on ‎07-03-2012 10:16 AM

When using external ram on the FlexRIO products it would be nice to have a memory map tool built into LabVIEW FPGA.

Many traditional FPGA release processes for companies require a memory map. Currently LabVIEW only allows the user to create memory partitions, but the user has no control on where the partitions are laid out in memory.

 

This can cause problems during the release process because the simulation is not repeatable because the memory element being accessed may be in a different location.

 

This feature will not impact the functionality of LabVIEW, but will make it easier to use LabVIEW FPGA in companies where Verilog, and VHDL languages were the only options for FPGA's and the release process is hard to change.

 

Hello Everyone

I am Muhammad Was,

an AE from NIJ.

 

While choosing FPGA variable, We should have sorted variable list for FPGA Read/Write Control option as we have in shared variable list that is always sorted and from A to Z.

 

In FPGA Read/Write Control option, variable added lately in FPGA VI, get higher position than old ones in the list.

Its voice of one of our FPGA customer.

 

Thanks and regards,

 

Waqas

 

Manzolli

Index to NI 9802 port access

Status: New
by Active Participant Manzolli on ‎03-30-2010 08:47 AM

The NI 9802 (Secure Digital Removable Storage Module for CompactRIO) is a cRIO module that has two SD memory card slots. The problem is that the programmer cannot index the ports as "0" and "1". The solution is to write a code for "0" and repeat it for "1".

 

The proposal is to allow the user to select memory card by a terminal in the "Method" and "Property" nodes.

 

Since the maximum amount of memory per card is 2 GB, if more than 2 GB is needed, the programmer should manage to split the data in two cards. Right now the code should be duplicated and selected by a "Case" structure. In many other situations the programmer may need to use one or other card, like when a big file should be saved after the usual check of the available free space in both cards.

 

 

0 Kudos

Make DRAM on sbRIO expandable on new and legacy sbRIOs. Add USB for connectivity, add more I/O expansion for 0-3, 0-5 and 0- 24 VDC.

 

sbRIO is pricey even for quantities. 35% profit margin should be fine.

0 Kudos
Student_Novice

VHDL Labview & FPGA

Status: New
by Member Student_Novice on ‎04-19-2012 09:23 PM

DC to DC converter basics using Labview for VHDL to FPGA Control 

 

I am fairly a novice, that is why simplifications required, before I begin thanks for them who will response in advance

 

I am designing a DC to DC (Intermediate Bus Converter, a step down BUCK converter, of 24 v input and output 9 v and 5 amp current), By using FPGA controller, having limited knowledge, I need to program this using VHDL, for which I take LabVIEW, but as I am new so do not have any idea as what are the steps that I need to take for implementation, what function that FPGA does in this so that it can generate 24 v and what other mechanisms that have to control inside or outside FPGA that it can give the desired output voltage, if you have any idea about this then I would be glad to receive the steps that are necessary to complete this 

About LabVIEW FPGA Idea Exchange

Have a LabVIEW FPGA Idea?

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