From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

LabVIEW FPGA Idea Exchange

cancel
Showing results for 
Search instead for 
Did you mean: 
0 Kudos
CrisSTine01

erreur lors de la compilation de l'FPGA

Status: New

bonjour, 

Voici l'erreur que j'obtiens quand je veux compiler mon programme FPGA

 

 

LabVIEW FPGA: La compilation a échoué à cause d'une erreur Xilinx.

Details:
ERROR:Pack:2310 - Too many comps of type "SLICE" found to fit this device.

Design Summary:
Number of errors: 1
Number of warnings: 89
Logic Utilization:
Number of Slice Flip Flops: 7,963 out of 10,240 77%
Number of 4 input LUTs: 10,607 out of 10,240 103% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 5,523 out of 5,120 107% (OVERMAPPED)
Number of Slices containing only related logic: 4,143 out of 5,523 75%
Number of Slices containing unrelated logic: 1,380 out of 5,523 24%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 11,028 out of 10,240 107% (OVERMAPPED)
Number used as logic: 10,454
Number used as a route-thru: 421
Number used as 16x1 RAMs: 70
Number used as Shift registers: 83
Number of bonded IOBs: 90 out of 324 27%
IOB Flip Flops: 97
Number of MULT18X18s: 38 out of 40 95%
Number of BUFGMUXs: 2 out of 16 12%

Peak Memory Usage: 359 MB
Total REAL time to MAP completion: 19 secs
Total CPU time to MAP completion: 19 

 

voici une capture ecran du programme 

merci d'avance 🙂

1 Comment
RavensFan
Knight of NI

Wrong forum.  This is for new ideas for LabVIEW FPGA.

 

You need to post in the French LabVIEW forum.  Discussions au sujet de NI LabVIEW