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spsimona

Smart compilation

Status: New

Hi there,

 

I got following feedback from a LV FPGA user:

 

When developing a FPGA application in LabVIEW, after submiting a FPGA code compilation - usually quite a lengthy process - if you modify the code either on the Front Panel or Block Diagram while compiling is in progress, this results in a Compilation Error at the end.


And this occurs regardless the modification be only a mere cosmetic change, without any implication in the code that is being compiled.
This is quite frustrating when you realize that the compilation has failed (maybe after half an hour waiting) just because you unconsciously clicked and resized some control or node.

 

In such a situation, when LabVIEW detects a code change while the FPGA compilation is running, it should warn the user with a message box; if the user confirms the code change, the current compilation can be inmediately aborted or let it continue (at user option); on the other hand, if the user cancels the modification, nothing happens and the compilation continues to a successful (hopefully) end.

 

 

Thanks

Álvaro

Álvaro Simón
Spain TSE | CLD, CTA & CPI
2 Comments
JCC_(SK)
Active Participant

Before each compilation I change VI property to Lock VI without password (then Save and then compile).

 

This lock will not allow me to change VI during compilation (this never happened) and mainly during run (this use to happen often).

 

spsimona
NI Employee (retired)

Hi JCC_(SK),

 

Thanks for your help.

The workaround you mentioned works.

 

From my point of view this workaround is not enough although solves the problem.

Why? There is not any KB or documentation that suggest that behaviour.

 

I guess we should take into account customer feedback for improving that feacture in next LabVIEW version.

 

 

Best,

Álvaro

Álvaro Simón
Spain TSE | CLD, CTA & CPI