I would like to see some form of simple locking mechanism for VIs that are targeted to an FPGA.
The use case would be where you have compiled a VI for your FPGA target and are currently in the process of debugging/testing it. While running interactively and opening and closing VIs, you accidentally move something on a block diagram without realizing it. The next time you hit the run button LV shows you the "Generating Intermediate Files" dialog and you have now ventured down the one way street to a full FPGA recompile.
I know that source code control or setting all files to read only would also work, but when debugging a project, it is cumbersome to continually check all files in and out, or to continually change the directory attributes.
Just a simple lock/unlock button on the toolbar to keep from shooting myself in the foot while debugging.
....posted as I sit here waiting on a 4 hour FPGA compile for just this reason.
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