Simple code lock for FPGA targeted VIs

[gsussman]

I would like to see some form of simple locking mechanism for VIs that are targeted to an FPGA.

The use case would be where you have compiled a VI for your FPGA target and are currently in the process of debugging/testing it. While running interactively and opening and closing VIs, you accidentally move something on a block diagram without realizing it. The next time you hit the run button LV shows you the "Generating Intermediate Files" dialog and you have now ventured down the one way street to a full FPGA recompile.

I know that source code control or setting all files to read only would also work, but when debugging a project, it is cumbersome to continually check all files in and out, or to continually change the directory attributes.

Just a simple lock/unlock button on the toolbar to keep from shooting myself in the foot while debugging.

....posted as I sit here waiting on a 4 hour FPGA compile for just this reason.

[Donovan_B]

I've run into this on several occasions too and I think this is a really good idea.

To avoid sitting through the compilation if you just want to cancel the changes you've made, you should be prompted to save any changes and you can choose not to save the changes, which will cancel the compile.  You can then go to File»Revert and any changes you've accidentally made will be erased and no recompile will be necessary.

[gsussman]

The problem becomes much less clear when you are working on something like a cRIO application.

I often times have both RT and FPGA code open at the same time.

If I make a change on the RT side of things, generally I am inclined to perform a "Save All" to keep LabVIEW from nagging me individually about every VI that is different. At that point, it is "Game Over" and you are committed to a recompile.