LabVIEW FPGA Idea Exchange

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dedrich@sara.com

Floating point FXD

Status: New

I find that I'm using large bit FXD to handle the dynamic range, but I only have 8 or 16 bit significant bits.  I have an I2S input of 24bit numbers that I store in memory as U16 with the following incoding Number = A*2^(B), where A is a FXD(+/-11,9) and B is a FXD(+/-5,5).  A and B are bit spliced array that form the U16.  This allows me a 33% memory reduction covering a greater dynamic range by trading off resolution.  Here the I2S input allows the counting of leading zeros or ones to create the number B and conversion back to 24bits is easy.  Three items would make this a great help: 1. a typedef, 2. a quick forward convertor from standard form to FP FXD, and 3. gain inputs on math elements such as FFT if they canhandle FP values.

2 Comments
Intaris
Proven Zealot

So you mean IEEE 754 Floating point support, also known as "SGL" on FPGA?

This has been available on LV FPGA for a while now (at least since LV 2012).

jiangliang
Member

I think PO is trying to say something like this:

 

https://en.wikipedia.org/wiki/Half-precision_floating-point_format

 

I myself found this would be very useful when dealing with image data, which a mostly U8, and you will need to do certain operation need just enough precision, and you know your data is not going too far from certain range.

 

LV FPGA does support a little bit of SGL, but not yet support half-precision floating point, which might came handy at sometimes.

 

Also, according to xilinx, there is a Floating-Point Operator core around, and it does support many kind of floating point data.