Access FPGA conditional disable symbols from Host VI

[solarsd]

Hi,

I find Conditional Disable Symbols in FPGA code very useful especially in a R&D environment where needs and code change back and forth rapidly. However, I also find it hard to keep track of all these changes. I propose to add support for reading FPGA Conditional Disable Symbols from Host to enable VIs like "Is_FPGA_Function_A_Enabled.vi" that would allow for the Host program to know the state (hardware revision of sorts) of the FPGA bitfile and adapt.

I'll give an example to illustrate this proposal.

Function A is implemented in FPGA bitfile v1. Function B is implemented in Host and is based on multiple calls to Function A. Your boss now wants Function B implemented in FPGA for performance reasons with means to disable the code if required. For this you define a Conditional Disable Symbol in the FPGA project "FPGA_WITH_FUNC_B" and write FPGA code for FPGA bitfile v2. Switching between v1 and v2 is easy enough from the project manager, but for the Host side there's no way of knowing whether Function B is implemented directly in the FPGA or should be "emulated" via Function A as before. If you could do a check like "if FPGA_WITH_FUNC_B == TRUE" you could easily make the Host aware of this.

Regards,

solarsd

[T-REX$]

Hey solarsd,

As long as the Conditional Disable Symbols haven't changed in the project since the last compile, this is possible to do through VI Server (since the project holds the symbols). Check out the very last post here by "Dan DeFriese" (http://lavag.org/topic/7454-conditional-disable-in-build-settings/page-2). The example he posted shows how to programmatically write symbols, but there is also a "Read Tag" invoke method that you can use.

I don't think this completely satisfies your idea, as the "state" of the symbols isn't saved in the bitfile in anyway... so you can only query possibly out of date information.

Anyway, hope that helps!

[Dragis]

There is also a good discussion about this topic here: http://forums.ni.com/t5/LabVIEW/Accessing-FPGA-conditional-disable-symbols-from-the-host-machine/td-.... In short, the conditional disable symbols currently in the project don't tell you what they were when a particular bitfile was created. They may not even mean exactly the same thing anymore. The safest way to deal with these symbols is to use them on the FPGA to populate a set of control registers you can then later query from the host interface. You are then guaranteed the bitfile will behave the way you expect it to.

PS. I realize you started that discussion solarsd, just wanted to point it out for others : )