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The Tick Count function in LabVIEW FPGA
can represent time periods with tick count accuracy of up to 2^32 clock
cycles, that is (using the standard 40 MHz FPGA clock) about 107
seconds.
Sometimes I need to handle longer time spans, and I use this example.
I suggest to implement a built-in 64-bit tick counter.
i like the idea, but i think we should take it a step further and allow the user to wire a constant 'max count' into the node. the internal counter can then be optimized to use the fewest bits necessary to meet that criteria.