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Power quality application (cRIO) SAR Read from FIFO.vi problem

Hello Smiley Happy,

i've been working on power quality messurements in labview 2016 , i have power quality add-on instaled on my labview, im also using crio-9074 module,and analog inputs 9225 and 9227, in power quality application sample section, there is a project named Power quality application (cRIO) SAR.lvproj, as part of it is subfolder in RT  named Read from FIFO.vi part of magnitude and frequency.vi, im stuck on one detail and i hope someone can solve it form me, in provided picture 1. red circle is a part that i dont understand what's going on, as i can se the data from fifo are transforemed in matrix, and than one part of matrix is sumed and multiplide with samples per circle (in this case 192) frequency is 50HZ and on part 2. red circle  we got sample rate in Hz wich in this particular case when you double click on sample rate indicator is 9600, can someone explain mi what is purpose of these blocks, and how do we get exact number of 9600 for sample rate in Hz i would be really greatful.

Greetings from Croatia Smiley Happy)

 

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Hello Simela,

 

Greetings from the UK!

My first point is a slight tangent. For the modules you are using you should actually start from the delta-sigma examples. Delta-sigma and SAR modules use different ADC technology which needs different FPGA applications so beware of that.

 

To answer your question directly though:

 

As you say the data from the FPGA is transformed into an array. This means that each channel is a column. It then takes removes the first column from the data and uses it to calculate the sample rate. Looking on the FPGA at block 9 this channel is actually the measured frequency from the resampling algorithm.

 

So they average this to get the average system frequency and then multiply the samples per electrical cycle to get the average samples/second.

This has to be done since the resampler on the FPGA adjusts it's output sample rate to the electrical system frequency so you have a fixed-angle sampling (or fixed number of samples per cycle). This can be frustrating for the programmer since we are used to a fixed sample rate! But it is important for the proper analysis of harmonic information

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
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Thank you on your fast replay James, you really did clear out some things for me instantly. As i am labview and cRIO newbie could you explain me why is for my analog inputs modules better option delta-sigma modulation then SAR, as i could understand about these modulations, delta-sigma has better resulution, but its slower then SAR, i didnt know that my analog modules affect witch method to use. Also my first task is to know to how target to host data exchange works, as ive seen on forum there is a lot of talk about DMA FIFO's and a lot of examples are provided, but as i can tell most of them are host(computer) to target(FPGA) related, i would like to know more about FPGA -HOST(RT cRIO) DMA FIFO transfers, do you have any good recomandation where to start, or some basic sample to see how that conection works.

Thank you in advance,

best regards Ivo

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Hi Ivo,

 

So it is because your modules are delta-sigma. It isn't a choice per module but rather some modules use delta-sigma ADCs and some modules use SAR ADCs so you have to match what you have. There is not much difference from the programming but basically the acquisition loop needs timing for the SAR since it requests a new sample each time. With the delta-sigma the rate must be set at the start and then you need no timing because the loop will wait for a new sample.

 

To learn more on the DMA transfers the compactRIO developer guide should give you a fairly good starter. You can find the FPGA section at https://www.ni.com/compactriodevguide/sec3.htm

 

Cheers,

James

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
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Thank you James, really nice explanation on FIFO functions, i was wondering if you or someone else on ni forums has any knowlage on how zero crossing method works in power quality application, as i can see it has allready been some talk on these subject, but it was not so understandable for me.If you could point out some most important aspects of these method and how it works i would be very greatfull,as i was serching internet for soultion, for easy understanding of method there is like 0 explanations.

 

zerocrossingvi.jpg

zerocrosing1vi.jpg

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