Has anyone used the Electric Power Suite successfully?

[Noriker]

We tested the example "Power Quality Applications(FPGA 50Hz)" of EPS. However the example program produces wrong results. We couldn't explain the reason. If anyone has used EPS, please help. To test, we wired one phase power supply.

[ThreeLions]

Hello,

Could you please describe the wrong result specifically? Is there an error code? Some screenshots are useful if possible.

Thanks!

[Noriker]

Hello, thanks for your reply.

There is no error code. The program runs but produce wrong results. We are mainly interested in frequency and power. The attached two screenshots show the setting, wiring and results. We connected to normal household power supply which has 50Hz frequency. We have changed module data rate, but it made no different.

The results shows the frequency measured on FPGA and RT are different and well away from the true value 50Hz. The voltage RMS seems reasonable.

We could use 3-phase PLL to measure frequency? Any suggestions?

Many thanks for your help.

[Noriker]

Sorry, forgot the attachemnet.

[James_McN]

Hi Noriker,

There looks to be a discrepancy in channel settings which are probably causing issues. You tell the resampler there are two channels in the resampling loop but in the top loop you still sample from 7. These numbers need to agree for the resampler to work correctly.

Cheers,

James

[MikolajM]

Hi James, 

that is not the issue, they have chosen a different value for the enum (2 channels) on the front panel. The case structure is not displayed on the case that will actually be in use, but on the default one. 

I do not have any constructive input for now, but I know that it will not be the issue.

[James_McN]

Hi Mikolaj,

I'm not sure that is correct.

In the data communication loop then the enum will change and not transmit unwanted channels to the host but the DAQ loop will always send 7 channels to the resampler due to the fixed build array. However the input to the resampler has been specified 2 input channels at that stage which means that the channels are going to get mixed up in the algorithm.

Unless you change the DAQ loop to input less channels I think the resampler should always be set to 7 and then the additional unwanted channels filtered in the communication loop.

I would also use a fixed reference channel number since we found a bug in the channel switcher - I don't think it is causing issues yet but it might in the future.

Cheers,

James

[MikolajM]

Hi James,

I think you are right here, the constant should just be kept at 7 and the case structure before the comms loop does the work in removing unnecessary channels. 

The channel switcher is an issue, I still have your fixed VI if that fixes the issue. But again, as you said it doesn't seem to be the root cause here. 

Do ou think it may work better (performance and error-resistance) if the DAQ loop is modified to handle only two channels?

Cheers,

Nick

[James_McN]

Hi Nick,

You are not going to get any noticeable performance improvement by removing input channels since the FPGA either manages the throughput or doesn't. Similarly with the errors.

It will save FPGA resources and compile times so if only 2 channels are ever needed you might as well remove the others but I would focus on getting this working as it is first in case new problems are introduced.

Cheers,

James

[Noriker]

Hi James and Nick,

Thanks very much for your help. We managed to have the frequency measurement  close to 50Hz (about 2% error) on RT but the frequency output of resampling VI on FPGA is around 40Hz still. This is not right, is it? For us it is important to measure frequency acurately on FPGA. Any suggestions?

Jenny