I need to increase the sample rate to 50KHz to allow for arc detection

[Gary_MavSysInc]

In an effort to get our arc detection software running we need to capture data with a sampling rate greater than 10kHz. Would setting the 'samples per cycle' to 512 (as opposed to 192) would allow us to use your re-sampled data at the RT-Controller (permitting us to use the FPGA VI un-altered) at a sample rate greater than 50KHz?

[QiaoGuo]

The number of samples per cycle can be specified from 128 to 512 without having to recompiling the FPGA VI. But even with 512 samples per cycle, the sampling rate after resampling is about 512*50 or 512*60, still less than 50k Hz.

Could that meet your arc detection requirement?