Hi, I am running the synchrophasor example from the Electrical Power Suite in Labview 2014 in order to implement a PMU unit. I am using a cRIO 9082 with the analog voltage and current modules 9225 and 9227
The main vi (Synchrophasor Measurement) runs only for 10 seconds measuring perfectly analog input data, on the next 10 it stops to read, and on the next 40 it freezes, then it starts all over again.
We modified the FPGA vi (The one who runs in the FPGA Target) and eliminated the GPS inputs, because we don't have the 9467 GPS module, the analog measurement is still the same and has not been modified.
It throws an error in the Read from FIFO vi:
"ep_Synchrophasor.lvlib:pmu_Read from FIFO.vi:7210001<ERR>Read Timeout: This error occurs if the Read VI does not receive all the requested samples before the user specified timeout period. Make sure the FPGA VI was started or increase the timeout."
We think that the FIFO reading vi is experiencing timeout issues, and we didn't modify the read FIFO vi.
Someone has tested this example? Does it works fine?
Thanks to anyone who can help me
