05-13-2010 12:00 PM
In 8.6 you can generate the IP from the Xilinx tools and then use the CLIP Node to import the IP into LabVIEW FPGA. It is more involved than the new IP Integration Node experience, but it is still a very flexible way of integrating external IP. Here is a doc that goes through CLIP Importation: http://zone.ni.com/devzone/cda/tut/p/id/7444
Also, if you are still current on your software service (SSP) you can also upgrade to the latest LabVIEW version at no cost. If you purchased 8.6 (or 8.6.1)
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
12-06-2010 12:30 AM
Hello Rick K:
Are there any IP that shows or points to a direction where a "digital, parallel I/O or high speed LVDS output from camera imager sensor" can be "deserialized/serialized" to produce a frame or image file? Our application is in the automotive camera hardware were usually proprietary and often times custom design hardware is used. It is neither of the usual camera standards (GigE, Firewire etc.) used but instead based on low level imager sensor protocols. In a sense what I needed is a "reconfigurable framegrabber" which can be flexible enough to accomodate image sensors from ST Micron, Aptina, Omnivision etc.
In my mind a FlexRIO with an adapter board (for the physical layer realization of the signals) controlled on a real time embedded controller on a PXI should be able to cut it - for the speed at least. However, to actually be able to write code to "serialize and/or deserialize" Horizontal and Vertical clocking, Image Frames, Synch is really to me an IP thing.
Thanks for any information that will lead me to the solution of this design problem.
12-08-2010 09:56 PM
Hi Rick K:
I simply saw a "at" reply?