Thank you for your feedback. This is exactly the type of information that I was looking for.
I'll chime in very late. If any of this was implemented in 8.5 and I don't know about it yet, I apologize.
The floating point functions would be useful. There are cases where space is not a major concern, and the floating point functions would be ideal for simplifying the logic.
I would like some sort of indicator that shows how many nsec each function or operation will take in a (timed) loop. It would also be nice to see a critical path indicated that shows the slowest sequence of operations in the loop. These improvements would make it much easier to optimize the process and maximize the loop clock frequency. I would understand if the values had to be approximate and would not be guaranteed by the compiler.
I like the idea of being able to indicate the space each function or operation takes. This would be very useful when trying to optimize the total size of the program.
As long as we are making a wish list, I would like it if more pre-compiling could be done by LabVIEW so the Xilinx compiler wouldn't take so long. I hate making a minor change to one routine and having to wait for the whole thing to compile over again. Perhaps if LabVIEW could keep intermediate code for the unchanged routines, so those portions only required the final integration with the new code.
It would also be nice to see a knowledge base article about implementing modified clocks. Until talking to an experienced NI programmer, I didn't realize the digital inputs on a RIO PCI board could be read at faster rates than the standard 40 MHz clock. By optimizing the read loop, we were able to get the clock speed up to 100 MHz. If I hadn't needed to use a FIFO buffer to get selected data out of the loop, it probably could have gotten closer to 200 MHz, which is what my customer originally wanted.
I just began to work on FPGA using LabVIEW 8.6.
Is there any updated library for floating pont for this version, by taking advantage that 8.6 can work on Fixed Point calculations of the FPGA? Please advise.