RTS output and Visa write not in sequence

[pavanb]

I am asserting RTS, writing and unasserting RTS, as shown below. unassert/assert state doesn't matter, RTS write is happening out of sequence.

 However on the scope I can see write starts, then RTS is asserted and quickly unasserted before write completes. I tried synch and asynch write and just put a sequence frame to no avail. VI is attached. Please help. Thanks. 

[Puchkov]

Might want to check the following links:

How Can I Control the DTR and RTS Serial Lines in LabVIEW?

http://digital.ni.com/public.nsf/allkb/1ECEFAA7AD52994986256966005356EA

LabVIEW VISA Open/Close Session Asserts Serial DTS

http://208.74.204.114/t5/LabVIEW/Labview-VISA-Open-Close-Session-Asserts-Serial-DTS/td-p/1163857

[pavanb]

Thanks, yes, I am aware of the first link and the second link doesn't apply. The actual scope sequence doesn't match the VI/software.