NAT9914 Hardware Interface Design

[RonS]

I'm designing a GPIB interface using the NAT9914. In the AN-110 Application note, there is a schematic that shows how to connect the 75160 GPIB transceiver to the NAT9914 (schematic on page 4). HOWEVER, in the NAT9914 Reference Manual (page 7-6) there is a different schematic. There is an additional OR gate between the NAT9914 (EOI and ATN signals) and the PE control of the 75160. Which schematic is correct? (And why do you think your choice is the correct one?)

Thanks in advance for your reponse!!

[GPIB_Guru]

"When this control input, denoted PE, is in the high
state, the bus outputs operate in the high-speed totem-pole mode. When PE is in the low state, the bus outputs operate as open collector outputs which are necessary for parallel polling."

This is from a DS75160 data sheet. The reverse logic of GPIB and the OR gate will automatically convert the 75160 to open collector when a parallel poll is occurring (ATN and EOI logically asserted). You should probably follow the NAT9914 manual since it handles the parallel poll case correctly.