Is there a schematic for TNT5002 cpu bus interface in GEN4882 mode?

[mike@ousetech.co.uk]

I have been given a GPIB PCB which uses a TNT5002 chip.  However, I am having trouble reading the registers using a TI Omap-138 CPU with the board attached to the CPU's EMIFA bus interface.

In particular, I believe that the PCB I have does not use HWORD properly.  Unfortunately, the information in the TNT5002 Tech Ref is vague and I have not been able to find anything on the NI site or elsewhere on the internet which shows the TNT5002 correclty wired up.  Apparently there was once an example schematic but it no longer exists anywhere.

[yytseng]

http://www.ni.com/pdf/manuals/370595b.pdf

Generic mode page2-8
A-6~A-9 for timing critical.

[mike@ousetech.co.uk]

Thanks for your help.  

Unfortunately, I have read these sections over and over without much luck!  The main point of interest is HWORD# which is described as being asserted during a 16-bit access and unasserted during an 8-bit access.  The person who designed the GPIB circuit has tied HWORD# to ground permanently since the bus it is designed to sit on is 16-bit.  

However, another interpretation of HWORD# is that it is an extra address line i.e. is A0 of the overall bus (especially as figures A-1 and A-2 show HWORD# as being treated like an address line with the same timings), with cpu A0 being A1 to the TNT5002.  If figures A-1 and A2 had been clearer it would have helped! 

As it is at the moment, I have checked that CS# and RD# have the correct timings but only read back zeros from the chip.  So next I might try tying HWORD# low to see if I can at least do 8-bit reads.

[yytseng]

I would like to suggest NAT9914 for 8bits data bus design.

it will be easier.

TNT5002 is a powerful GPIB chip for modern processor, except using 8bits data bus.

In your case, you will need a glue-logic for interface this data bus.