Enabling interrupts should not have an affect. Can you give me a summary of how you are setting up the chip? For example, what are you setting in the ADR register? This register sets the addressing mode of the chip. If you are not setting it up correctly at address 3, you would, of course, not get an interrupt.
So, lets assume you are setup correctly. There are a couple of different things to try.
1) You can look at the MAC bit in ISR0. This is the My Address Changed bit, which should set everytime your addressing mode changes.
2) Note that the NAT9914 does not have static bits in the ISR registers. If you read a register, the bit will clear automatically. Just in case something else asserted along with MA and you hand
led it but forgot to check MA, you will lose it.
3) You can try setting MA IE. This will not generate an interrupt if you have interrupts disabled, but it will cause an NDAC holdoff. In this case, the ibrd 100 should timeout on the host side if the device is actually doing the holdoff.