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Generating VHDL from Graphical Logic Gates?

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I've been going around demonstrating the Digital System Development Board to professors looking to implement a hardware focused digital electronics course and I had an interesting question: "Can I show students the VHDL code generated before programming the FPGA?" My position has always been that students learning the basics of digital electronics need to focus on the logic blocks and what they do rather than trying to learn a programming language but I am starting to understand that the transition from graphical logic blocks to actual HDL coding is very often overlooked.

 

In case you didn't know, many schools and universities, like Project Lead the Way use Multisim to directly program FPGA development boards so that students can measure and see the digital logic circuit working without having to troubleshoot their way through messy 74-series logic chips and without learning a new programming language. Students put gates after gates and then just click transfer to fully immerse themselves in the logic.

MS_Digital_Logic.png

 

This method of programming generally challenges schools to reconsider whether digital logic and an HDL should be taught together in the same course or whether there is room to begin with logic gates then move to VHDL or Verilog in a separate, more advanced course.

 

Back to the professor asking about generating VHDL code from Multisim. The answer is yes. What I am now beginning to realize is that some students will end up needing experience in HDLs when they graduate so colleges and universities preparing students for those jobs will need to expose students to HDLs sometime during an introductory or advanced digital logic course. For me, a fantastic way of making the switch from logic blocks to VHDL is to compare 1:1 the design built from logic blocks in Multisim and the VHDL code that is generated.

 

Here's how to do it:

Begin your FPGA design by opening a new blank workspace in Multisim. We will then add our FPGA interface by going to Place->New PLD Subcircuit. Working through the prompts you will select which FPGA to program then select which FPGA pins to place.

PLD.png

 

This creates the FPGA block that we will be programming within. Using the workspace you are in now, simulated signals can be substituted for real signals as inputs to the FPGA. Double-click the FPGA you just placed and click Open subsheet to begin programming the FPGA.

OpenPLD.png

 

Now that you are in the FPGA environment, begin to create the program by placing logic components and conneting the IO. Now normally at this point I would say transfer directly to your FPGA but remember, we are beginning our studies on VHDL so let's generate that VHDL code:

 

Select Transfer->Export to PLD then instead of selecting Program the connected PLD, select the Generate and save VHDL files option. 

VHDL.png

 

Viola! The VHDL code has been created!

VHDL_Code.png

 

Hopefully this is an easy way to teach digital logic AND introduce VHDL concepts all in the same course without devoting time to learning how to program. If you'd like an example to start from try this counter example using a 7-segment display.

Brian H. -- Electronics & Measurements Product Marketing Manager