We would like to apply 56MHz ext clock to PCI-5640R in order to align IQ data rate to IF=70MHz. It seems there are five control clusters in charge for such migration to ext. clock: CDC Clock Source; VCXO; Reference; PLL; and Routing
Most sensitive is only CDC_Clock_Source => Clock_Source.
It is very strange, that Y4 (RTSI Ref) divider does not demonstrate meaningful operation, but it should according to Timebase Block Diagram
Please advise how to solve the problem, and which values should be assigned to Config Timebase clusters' controls
I would like to refer you to the NI PCI-5640R Timebase content from the help documentation:
How have you connected the external clock? There is a CLK IN front panel connector, is this where you have the external clock coming in? The Y4 (RTSI Ref) is actually a ribbon connector on the 5640R board which will be on the inside of the PC. Is it possible for you to upload your code, so I can take a look at it? In order to use external clock, you will have to program in LabVIEW FPGA.