I am trying to perform a decimation operation in the fpga by capturing the outputs of a LPF
at a slower rate than the filter. My filter is running at 80MHz and I'm trying to capture the
data out of the filter at 40MHz (downsampling by 2) to complete the decimation operation.
The filter is in a single cycle timed loop and I'm looking at the data that is coming from that
filter using probes that are in the slower loop (running at 40MHz). What I see is that the
slower loop doesn't seem to be updating at the right rate. I was expecting to see every other
sample from the 80MHz loop enter the 40MHz loop. Instead I see a value that appears to be
held for several cycles.
I am using a local variable to pass the data between the 2 loops. The data seems to be
scaled. For example, leaving the 80MHz loop I see a value of -13.9375 on the local variable,,but when
I read that same variable in the 40MHz loop it appears to be -13.312.
I've attached the vi in case it helps.
Solved! Go to Solution.
I have not had a chance to thoroughly look at your code, but a few things come to my mind that may help. I believe you are running the code in emulation (execute on development computer) mode in order to debug. This is a helpful feature for finding logical errors, but there is no guarantee of timing in this mode. Therefore one cannot assume the 80MHz loop runs 2 iterations for every 1 iteration of the 40MHz loop. This could explain what you are seeing. I am making the assumption you are running in emulation mode because you have a -1 constant as an input on the FIFO nodes. This is not a valid setting when using the FIFO inside a Single Cycle Timed-Loop (SCTL). You must wire a constant 0 to the timeout of FIFOs inside. The reason for this is that the SCTL executes every iteration within one clock cycle in hardware. There cannot be any code that blocks within the SCTL. I would expect a code generation error from your code if you actually tried to compile. I realize this isn't very helpful information in terms of your issue, but thought you should know. Another tip is that there exists a Rational Resampler functionon the FPGA palette. You can find it under Programming>>FPGA Math and Analysis>>Rational Resampler. It can be configured for an integer decimation by setting L to 1 and M to 2. It will likely use more resources than your current implementation, but be pretty straightforward.
Thanks. I am aware of the -1 setting not working when running on the HW, but thanks for the reminder.
I think I've got things working with target-scoped FIFOs instead of the local variables. Definately more
resources so if I have time I may try the Rational Resampler. It might be a more efficient implementation.