I have not had a chance to thoroughly look at your code, but a few things come to my mind that may help. I believe you are running the code in emulation (execute on development computer) mode in order to debug. This is a helpful feature for finding logical errors, but there is no guarantee of timing in this mode. Therefore one cannot assume the 80MHz loop runs 2 iterations for every 1 iteration of the 40MHz loop. This could explain what you are seeing. I am making the assumption you are running in emulation mode because you have a -1 constant as an input on the FIFO nodes. This is not a valid setting when using the FIFO inside a Single Cycle Timed-Loop (SCTL). You must wire a constant 0 to the timeout of FIFOs inside. The reason for this is that the SCTL executes every iteration within one clock cycle in hardware. There cannot be any code that blocks within the SCTL. I would expect a code generation error from your code if you actually tried to compile. I realize this isn't very helpful information in terms of your issue, but thought you should know. Another tip is that there exists a Rational Resampler functionon the FPGA palette. You can find it under Programming>>FPGA Math and Analysis>>Rational Resampler. It can be configured for an integer decimation by setting L to 1 and M to 2. It will likely use more resources than your current implementation, but be pretty straightforward.