IF-RIO

[Jersey Chris]

Hi Jerry,

 Thanks again for your invaluable insight.  We are sending #0 to the Q portion of the 32-bit input into the DAC (configured for IQ) for simplicity.  The program that Andrew has posted is primarily for testing purposes.  

 Since we are using BPSK, a 180 degree offset is of interest to us.  However, we are performing this offset before passing the signal into the DAC.  For this purpose, isn't wiring #0 to the Q portion of 32-bit word sufficient?  

 You mentioned that an optimal DAC sampling rate is 200 Msamples/second and that the DAC sampling rate should match that of the IQ rate, which is A.O symbols /s x samples/ symbol.  However, in the example that I include, which uses the Analog Input and Output FPGA vi, the transmitted and received waveforms "match" to some extent, but the IQ rate is at 2M samples/s, which is not equal to the DAC sampling rate.  The A.O. sampling rate was determined purely by trial and error.  

 The question remains: why can't we get an close to exactly matching received analog signal?  This applies to the examples Andrew and I have posted.   

Regards,

Chris  

[Jerry_L]

Hi

The IQ Rate is 1.0 MSps, but the DAC clocked SCTL is running at 2 MSps because the I and Q samples are passed to the DAC IO node on every other clock sample.

J

[amuehlf2]

Jerry,

We have made a lot of progress over the weekend.  

1) We found that setting the CIC to 32 causes the frequency of the output of the ADC to match the frequency of the input to the DAC.  At this point, we have our BPSK receiver and transmitter both working in software, with only the transfer to and from ADC and DAC happening on the FPGA.

2) We succeeded in generating a sine wave on the FPGA itself, feeding it into the DAC, and reading it into software from the ADC.  Your links to posts describing the DAC_IQ Clock were especially helpful.  Thanks.

The Analog Input and Output example is somewhat overwhelming for a couple of Labview rookies (as of six weeks ago), but between your help, and enough hours staring at the code, we are steadily gaining a firm grasp on what each of the components of the example does.  I believe we are on track to a successful project.  Our next step is to modify our Costas loop to track the hardware generated sine wave.  Then, we will move our BPSK modulation to the FPGA, and we will be done. 

Thank you for all your help so far.  We will post again soon if we encounter any new mysteries.

- Andrew

[amuehlf2]

We have a BPSK transmitter working on the FPGA and a receiver working in hardware, passing through the DAC, wired and ADC.

The only flaw is that the FPGA to Host Read FIFO method seems to drop samples in between reads.  In other words, we read samples in groups of 5,000.  We receive 5,000 good, consecutive samples, and process them as expected.  However, the following grouping of samples does not begin at the 5,001st sample.  We would like to receive continuous data, rather than be limited to processing 5,000 samples of data.  Is it possible to do so with the Analog Input and Output example?  If so, what must we change?

I have attached the Host and FPGA VIs.  To demonstrate the discontinuity, the PN sequence is initialized to output only zeros, resulting in a pure sine wave.  The Host Front Panel is organized in three columns.  The second column has a graph titled "Two Consecutive FIFOs of Received Samples (Included to show transition)".  We store the previous group of data read from the FIFO, and concatenate it with the current data read from the FIFO to demonstrate the discontinuity.  I saved as default a set of example data.  It is a coincidence that the discontinuity is nearly a phase shift of 180 degrees.  The phase shift is different every time.

Thanks.

[Jerry_L]

Hi

The Input and Output example was not designed to do a continuous acquisition.  The host side of the program initiates an acquisition of a set number of samples, and then reads them back when acquired. The acquisition stops when the number of samples has been acquired.

The example will have to modified on the FPGA VI to do as you wish.  In the ADC loop, this involves removing the test case for the number of samples acquired which stops the acquisition so that is runs until you have a stop action stop it.

You have to do a similar action on the RTSI clock loop so that the loop does not stop when the number of samples has been transferred from the transfer FIFO. 

You might find this example helpful.
ftp://ftp.ni.com/support/rf_segment/demos/ifrio/ContinuousAcq/ni5640RSingleCHContinuousAcquisitionEx...
But, it is not in LV 8.6, so it may be hard to view correctly.

The other issue is that you have to make sure that your system can maintain a constant throughput at whatever you acquisition rate is.  If you can’t bring up the data to the host fast enough, you’ll lose data in the FIFOs overflowing. So, you should have some flags that you can read from the host when a FIFO overflows.

Jerry

[Jersey Chris]

Hi Jerry,

  Andrew and I demonstrated our project today for our digital signal procesing laboratory class and it was quite successful--students and professors were quite impressed with LabVIEW's capabilities.  We sincerely appreciate your help and superb responsiveness on such short notice.  In the near future, Andrew and I will be sharing documentation of our work throughout this project to assist future digital communications and digital signal processing laboratory classes with developing projects using the 5640R IF-RIO.  Thanks to you, our experience with LabVIEW turned to be a quite positive one. 

Regards,

Chris 

Electrical Engineering

University of Illinois at Urbana-Champaign

[cdschmit]

This post ended with recommendations on how to get continuous acquisition on the PCI ni5640r (IF RIO).  I wanted to cross-reference it with the postings at http://forums.ni.com/ni/board/message?board.id=280&message.id=8356#M8356 which provides code to solve this problem in LabVIEW 2009.

[kami70b]

how can i configure adc and dac to operate at 80 MHz clock rate and the fpga should also operate with this clock what i have to do in my design