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amuehlf2
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Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

I am a student at the University of Illinois, working with "Jersey Chris" on a communications project, using the PCI-NI5640R.  Chris asked several questions in a post earlier today, and after another long night in the lab, we are still struggling.

 

What we really need, though, is a set of example VIs that do the following:

 

Pass a user provided data stream from the Host, into the FPGA, then to the DAC and then AO.  Take that analog signal into AI, through a hard-wire, pass it to the ADC, and pass the digitized stream back to the Host.

 

If it is quick and simple, we would also benefit from a set of example VIs that show how the output of a sine wave generator within the FPGA vi can be sent to the DACs, for the sake of understanding how data creation synchronized with the DACs.    

 

Our entire project is functioning in software.  We have also been successful in putting some modules on the FPGA and passing data back to the Host.  Our last step is to interface with the DAC and ADC.  We spent about a month trying to do so, and we suspect that it would take one of the R&D foks a mere ten minutes to create such an example.  We have spoken to tech support, our university's NI rep, and the region's NI rep, and ultimately they have pointed us to you. 

 

Our project is due Wednesday, May 6th.  Any help would be greatly appreciated. 

 

Thanks,

 

- Andrew Muehlfeld

University of Illinois at Urbana Champaign, Student

 

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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

Hi Andrew, 

 

It seems as though you are using the correct example program to start from but have modified it such that it does not behave as expected. The first thing that I noticed is that you have removed the while loop from the host which will cause the vi to only poll one time, is this what you want? Does the unmodified example work correctly on your system? What exactly do you need that is different from the example? Based on your description of the example you would like it seems that you already have it. If you could clarify exactly why that example is not helpful it would give us a better understanding of how to approach this.

 

 

JaceD
Signal Sources Product Support Engineer
National Instruments
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Jersey Chris
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

The first thing that I noticed is that you have removed the while loop from the host which will cause the vi to only poll one time, is this what you want?

 

I was under the impression that the while loop is used for the acquisition of the analog input signal, but apparently it is necessary to include the while loop to be able to observe something on the oscilloscope.  I am more concerned, however, with being able to send a custom signal through the DAC. We have tried doing so from the host, not the FPGA, unsuccessfully. 

 

I will try including a while loop at the host.  Can we now expect the DAC to output the correct signal?  Or are we still missing something?  The issue, as mentioned on the other post, is that the program only executes properly every second time.  

 

 

Does the unmodified example work correctly on your system?

Yes, as do the other examples included.  

 

What exactly do you need that is different from the example?

We need to output a BPSK waveform, which is a sine wave with 180 degree phase shifts at the appropriate instances.  As seen in FPGA I posted, we are trying to accomplish this through the sine-wave generator VI at the FPGA and then setting a center frequency of 0 at the DAC.  

 

Another possible way (though we have not tried it yet), would be to treat the center frequency as the carrier frequency and modulate a square wave of +/-1.  This may be a better way, but we still don't fully understand how to output a custom signal on the DAC.  Hence the desire for another example. In the context of Andrew's post, this may entail sending a sawtooth or triangle wave through the analog output.  

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amuehlf2
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

We have made some big progress.  After your confirmation that the Analog Input and Output example does indeed do what we want to do, we started from scratch, again, using that example.  We were able to accomplish something close to what we want.  We can pass our signal through the output and back into the input.  It is clear that the signal is based on the signal we are providing, but it is not quite identical.  I have attached a screenshot showing Raw Input (the input to the DAC, which then goes to AO), and Raw Output (the output of the ADC, which comes from AI).  I see two issues.  1) Their periods are not the same.  2) There is a blip.  What might cause this behavior?  (Our VI sends a pure sine wave, no BPSK modulation at this point.  We also do all processing on the host at this point).

 

I have attached the VI as well.  The FPGA bitfile is unmodified.

 

Thanks,

 

- Andrew
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amuehlf2
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

I believe I discovered the source of the blip.  The wave we are writing to the FIFO is ~10.5 periods of a sine wave, instead of an integer multiple.  The blip is of little concern, then, for the moment.  More importantly, what is the correct way to send a dynamic message, (rather than just repeating the one message written to the FIFO at the start)?
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Jerry_L
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

Hi

First off, are you aware that the data to the DAC is IQ complex data?  Not real data.

The data is sent to the DAC every other DAC clock period, I and Q samples interleaved.  The examples show how the data is interleaved after being split from a U32 data sample.  You have to ensure that your waveform is created for the DAC sample rate configured.

Unfortunately, as you have noticed, the sine block included with LV FPGA does not work in the Single Cycle Timed Loop (SCTL).  But you can create your own sine waves in the SCTL by creating your own DDS blocks.  I have an example of this in the attached VIs.  They create a package of FM tones.  There are two parts to this example.  A host side that calculates the DDS tuning words, and the FPGA VIs (4 Tone FM Modulation subVI_v01.vi).  Every clock cycle, a sample is created for the DAC.  Prior to starting generation, you need to calculate the frequency tuning word, etc on the host and write the values down to the FPGA.

A square wave is pretty close for a BPSK signal.  Just make the I waveform sample the +/- 1 and the Q can be be all zeros,  But make sure that you still download the zeros when the Q sample is expected.

I’m not sure what you are going to get though when passing this data to the DAC.  The data will be swinging 180 degrees instantaneously.  Typically the data is filtered before downloading.  Modulation Toolkit can create the filters for you depending on your parameter.  (Who is your NI Representative?  Does he have experience with the IF-RIO?)

Continuous generation from the host to the FPGA and then to the DAC is a balancing act.  You have to make sure that the DAC rate is not so high that you do not start the DAC for data.  So, the download rate to the FPGA must be faster than the DAC rate, and you need to continually download data in a loop running on the Host VI.  On the FPAG, I would probably read the data from the Host to FPGA Read FIFO in a SCTL running off the RTSI clock running at a pretty high rate.  I would create a FIFP on the FPGA of a good size and write the data from the DMA FIFO to this FIFO.  The other end of this FIFO is in the DAC loop passing data to the DAC.  You need to set up some handshaking on the FPGA so that the DMA FIFO stops reading data from the Host when the FPGA FIFO fills up.  You also need a signal to start reading data from the FPGA FIFO in the DAC loop after the FIFO has been primed with a good number of samples.

Jerry
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amuehlf2
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

Jerry,

 

Thank you for your post.  It was very enlightening.  I will look at your examples when I get to the lab tomorrow.  From the sound of it, your example is exactly what we were looking for.

 

- Andrew

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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

We plugged in a look-up table to replace the sine generator, but have the same issue: when we pass a plain-vanilla sine wave into the DAC and read it out of the ADC on the other side, the period is different.  We found that when we modify the control "AO.Symbol Rate", which ultimately affects the "CIC Interpolation Factor" of the DAC, it changes the periodicity of the signal read from the ADC.  Can anyone explain the CIC Interpolation Factor to us, or point us to its documentation?  It perplexes me that a real-time system can stretch a signal in time, so I am clearly missing something fundamental.  How can we calculate what that value for CIC Interpolation Factor should be?  We can get close through trial and error, but we need to be precise. and we would also like the flexibility to change our BPSK carrier frequency in the future.  Is there a corresponding value on the ADC which must be configured to the same value so they match?

 

I have attached a barely-modified copy of the Analog Input and Output Host VI example.  We replaced the input to the DAC with a sine wave lookup table, and added two graphs to display the wave going int the DAC, and coming out of the ADC.

 

 Thanks,

 

- Andrew

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amuehlf2
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

And here is a screenshot of the periodicity mismatch.
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Jerry_L
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Re: Request for Example VIs: Pass Digitized Signal Direclty to DAC without Modulation, and Vice Versa

Hi

Concerning the clocking of the DAC’s single Cycle Timed Loop (SCTL) and passing data to the DACx IO Node on the FPGA, I suggest reading the following message topics.

Re: Configuring the IF-RIO's DAC channels
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=265&query.id=21964#M265

http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=149&query.id=22014#M149

I’m not able to run your VI now as I don’t have any hardware here.  It would have been good if you were able to save the graphs you are referring to with default data do I can see them results without running the program.  Unless you can wait until Monday.

But from what I see in the code, it looks more like you are going to generate an AM waveform, at least that is what you get when you make the I data samples a sinewave, and the Q data samples just zero.  It’s probably the simplest form of a complex waveform.  Other than just setting the I data to all 1.0s and the Q data to all 0.0s, which would result in just a sine at the output at the DACx’s NCO frequency.

From looking at the default values of the attached VI, it looks like the interpolation is set for 200.  There is an internal fixed interpolation of 4, so a 50 is written to the configuration VI on the host.  You are downloading 1000 samples of a waveform containing 6.x cycles of a waveform in the I data.  I’d guess that the output would be an AM DSB waveform (way over modulated as the sine swings from -1.0 to + 1.0, a 100% AM waveform would have the I data range from 0.0 to +1.0.) with the modulating sine at about 6 KHz.

If you want a sine at the output of the AO0, at a configured offset, you need two sinewaves in the I and Q data, at a 90 degree offset such as in the example.  This produces an offset from the configured NCO frequency at the frequency of the sine in the waveform taking into account the DAC IQ rate (1.00 MSps in this case.)

Jerry