I am a student at the University of Illinois, working with "Jersey Chris" on a communications project, using the PCI-NI5640R. Chris asked several questions in a post earlier today, and after another long night in the lab, we are still struggling.
What we really need, though, is a set of example VIs that do the following:
Pass a user provided data stream from the Host, into the FPGA, then to the DAC and then AO. Take that analog signal into AI, through a hard-wire, pass it to the ADC, and pass the digitized stream back to the Host.
If it is quick and simple, we would also benefit from a set of example VIs that show how the output of a sine wave generator within the FPGA vi can be sent to the DACs, for the sake of understanding how data creation synchronized with the DACs.
Our entire project is functioning in software. We have also been successful in putting some modules on the FPGA and passing data back to the Host. Our last step is to interface with the DAC and ADC. We spent about a month trying to do so, and we suspect that it would take one of the R&D foks a mere ten minutes to create such an example. We have spoken to tech support, our university's NI rep, and the region's NI rep, and ultimately they have pointed us to you.
Our project is due Wednesday, May 6th. Any help would be greatly appreciated.
- Andrew Muehlfeld
University of Illinois at Urbana Champaign, Student
It seems as though you are using the correct example program to start from but have modified it such that it does not behave as expected. The first thing that I noticed is that you have removed the while loop from the host which will cause the vi to only poll one time, is this what you want? Does the unmodified example work correctly on your system? What exactly do you need that is different from the example? Based on your description of the example you would like it seems that you already have it. If you could clarify exactly why that example is not helpful it would give us a better understanding of how to approach this.
The first thing that I noticed is that you have removed the while loop from the host which will cause the vi to only poll one time, is this what you want?
I was under the impression that the while loop is used for the acquisition of the analog input signal, but apparently it is necessary to include the while loop to be able to observe something on the oscilloscope. I am more concerned, however, with being able to send a custom signal through the DAC. We have tried doing so from the host, not the FPGA, unsuccessfully.
I will try including a while loop at the host. Can we now expect the DAC to output the correct signal? Or are we still missing something? The issue, as mentioned on the other post, is that the program only executes properly every second time.
Does the unmodified example work correctly on your system?
Yes, as do the other examples included.
What exactly do you need that is different from the example?
We need to output a BPSK waveform, which is a sine wave with 180 degree phase shifts at the appropriate instances. As seen in FPGA I posted, we are trying to accomplish this through the sine-wave generator VI at the FPGA and then setting a center frequency of 0 at the DAC.
Another possible way (though we have not tried it yet), would be to treat the center frequency as the carrier frequency and modulate a square wave of +/-1. This may be a better way, but we still don't fully understand how to output a custom signal on the DAC. Hence the desire for another example. In the context of Andrew's post, this may entail sending a sawtooth or triangle wave through the analog output.
We have made some big progress. After your confirmation that the Analog Input and Output example does indeed do what we want to do, we started from scratch, again, using that example. We were able to accomplish something close to what we want. We can pass our signal through the output and back into the input. It is clear that the signal is based on the signal we are providing, but it is not quite identical. I have attached a screenshot showing Raw Input (the input to the DAC, which then goes to AO), and Raw Output (the output of the ADC, which comes from AI). I see two issues. 1) Their periods are not the same. 2) There is a blip. What might cause this behavior? (Our VI sends a pure sine wave, no BPSK modulation at this point. We also do all processing on the host at this point).
I have attached the VI as well. The FPGA bitfile is unmodified.
Thank you for your post. It was very enlightening. I will look at your examples when I get to the lab tomorrow. From the sound of it, your example is exactly what we were looking for.
We plugged in a look-up table to replace the sine generator, but have the same issue: when we pass a plain-vanilla sine wave into the DAC and read it out of the ADC on the other side, the period is different. We found that when we modify the control "AO.Symbol Rate", which ultimately affects the "CIC Interpolation Factor" of the DAC, it changes the periodicity of the signal read from the ADC. Can anyone explain the CIC Interpolation Factor to us, or point us to its documentation? It perplexes me that a real-time system can stretch a signal in time, so I am clearly missing something fundamental. How can we calculate what that value for CIC Interpolation Factor should be? We can get close through trial and error, but we need to be precise. and we would also like the flexibility to change our BPSK carrier frequency in the future. Is there a corresponding value on the ADC which must be configured to the same value so they match?
I have attached a barely-modified copy of the Analog Input and Output Host VI example. We replaced the input to the DAC with a sine wave lookup table, and added two graphs to display the wave going int the DAC, and coming out of the ADC.