Hello I am using 5641 R Transceiver and 5600, 5610 to down up converters. What I wanna do is:
-downconvert the incoming signal an UMTS signal (with a power density of about -80dBm)
-using the FPGA I want to amplify the signal
-upconvert the signal
-transmit the amplified signal
I am compiling a really simple FPGA code to introduce a configurable linear gain
It works ok with a DIGITAL gain up to 2 (linear scale) but if I multiply the incoming signal with a higher value, the output power doesnt increase
I know I can use down and upconverter gain, but I also want to digitaly amplify the signal. (I want to get a power near -1.5 dbm at the output of the IF Transceiver, that is the maximium output according with specifications)
why is the maxomium scale factor 2 ??
(also the VI "NI 5640 DAC Config IQ" has an input called "output scaled factor", and its maximium value is 2 )
Solved! Go to Solution.
Hi I just realize that each multiplier can produce a gain of 2, next time I will try before asking, but still components should be more intelligent than users
Were you starting from one of the examples? I am not sure which multiplier you are talking about. If you are talking about the multiplier from the Process Data VI in the Analog Input and Output example, then it is not limited to multiply by 2. The reason it may seem that way is that the fixed point number that you are scaling by has been configured to have a word length of 18bits and a integer word length of 1bit. This means that the range would be 0-2 with a resolution of 7.6294e-6. You can right click on the fixed point number control and change this representation to have a different integer word length. For a given "Word Length", increasing the "Integer Word Length" will widen the range of values, but decrease the resolution that you can achieve.
Hope that helps. Let me know if I didn't understand your problem correctly.