Bandpass Filter for 5641R

[eton]

Hi,

I'm new to NI LabViw and FPGA. I had a project of using NI to do modulation.
I got a FPGA code for the modulation, however it generates a few harmonics very near to the centre frequency.

I tried to integrate a bandpass filter into the FPGA code by following the "Generating LabVIEW FPGA Code" tutorial, however it doesn't work.
I took the generated filter and integrated inside a VI which is within single-cycle Timed Loop of 2.5MHz.

Is there a step by step guide on how to create a filter for FPGA or any examples?
I found a lot of examples but not for FPGA code.

Or do you have any better solution to remove the harmonics?

I have:
1) PXIe-5641R (Take in a 9600kps TTL signal from DIO and modulate out 30MHz to CH0)
2) PXIe-6672 (Provide a 35MHz clock to 5641R)
3) Labview 2011
4) Digital Filter Design Toolkit

Thank you very much

[eton]

Hi everyone, 

Can anyone help me out?

Do you have an example of bandpass filter in the FPGA?

Thank you.

[JoshY]

Hi eton,

I believe there are several filters already built in as express functions on the LabVIEW FPGA palettes. These can be found by going to the Block Diagram then FPGA Math and Analysis. Depending on your application, you could combine two Butterworth filters or a Notch filter may suffice. Another option would be to search the Xilinx Coregen IP palette. Hope this helps!

[eton]

Hi Josh, 

Thank you for your reply.

I had tried the FPGA Math and Analysis - Butterworth Filter, however i could not set the cutoff frequency  of 30MHz. As the expected sampling rate can only set to 40MHz - the FPGA clock rate. Am I setting the correct configuration?

As for now, i will try the Xilinx Coregen IP.

Thank you.

[Dayna]

Hi eton,

You are most likely not setting the correct configuration.  This VI requires that you set both the FPGA clock rate and the Expected sample rate to at least double the Cutoff frequency.  Please see the image below for a proper configuration.

This is a requirement in order to satisfy the Nyquist Theorem.  For more information, please see this document: http://www.ni.com/white-paper/2709/en#toc4 .

I hope this helps!

Regards,

Dayna P.

Applications Engineer

National Instruments

[eton]

Hi Dayna, 

Thank you.

However, I could not compilate the FPGA code as the express filter could not supported in the single-cycle Timed Loop.

[Dayna]

Hi Eton,

You are correct.  The Butterworth Filter is not supported for the single-cycle timed loop.  See this help document for more information: http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpga/fpga_timed_loop/

Regards,

Dayna P.

Applications Engineer

National Instruments