'Timing violation' says, that your execution path at FPGA is too long to get executed within one clock.
Solution can be to break up the path with feedback nodes, at possible places. -> see http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_fix_timing_violations/
To your other problem: take as said maybe a look on https://decibel.ni.com/content/docs/DOC-4068 - and how it's done there. These are good examples, how standard modulation is done with FPGA + SCTL.
With streaming prepared data from host to client I have no experience- I've done so long all modulations and demodulations on FPGA. And the snippet you posted seems not very helpful for diagnosis, when output is unknown. -> Are you doing the right output method? With IFRIO you have to interleave your data. One clock I-part, next Q-part, and so one.
