03-23-2010 10:13 AM
Hello,
I've been slowly modifying the 5641R FM-Demod example, from the RF communications library, into an FM-Demod/Regen example. I essentially want to use the 5641R as a retransmitter with processing. I've successfully used the 5641R as a retransmitter without processing but I noticed that the retransmission of an FM-Demoded signal isn't as expected. Mainly because the output of the FM-Demod IP core is real valued and the D/A on the 5641R is configured for quadrature I/Q mode. So, Do I need to add another processing loop in order to recreate IQ data and if so...how? I'm familiar with the concept of IQ and how to generate it but I'm fairly new to FPGA development as well as Fixed Point so I haven't been able to figure out how to accomplish it on the FPGA. Is there some sort of "MT Upconvert baseband to IQ" block for the FPGA?
Right now I'm essentially getting duplicated spectrum when regenerating the FM-demoded samples. For example, a 4fsk signal becomes 2 tones mirrored on either side of the IF center frequency instead of 4 independent tones.
I've attached a snippet of the code below.
Regards,
Tim S.
Solved! Go to Solution.
03-23-2010 11:34 AM
Hi Tim,
I am a bit confused as to what you are trying to accomplish. Based on your description of what you expect to see, you are attempting to transmit the same signal as you received which is a 4FSK modulated signal. Is this correct? If so let us look at what you have, From the ADC you receive IQ data containing your 4FSK signal, then you processes this through the FM-Demod vi, which outputs a real stream of your information signal. At this point if you want to transmit this data you would need to modulate this information signal to a 4FSK IQ signal and provide this to the DAC which would then transmit the same signal as you received. If you can also feed the IQ streams into the DAC which will accomplish the same goal but you will not have any processing which you have said that you need. I hope this helps, please let me know if I am incorrect.
03-23-2010 12:13 PM
Hi JaceD
Essentially what I'm trying to do is inject a Frequency Modulated signal into AI0, run it through the processing loop to FM-demod it, and then send out the FM-demodulated data using the AO0 port.
Maybe FSK was a bad example but what I did was pass a 4 fsk signal with 20kHz tone separation through "MT Modulate FM" with a peak frequency deviation of 75kHz. The resultant signal was generated using the PXIe-5672 VSG which is connected to the AI0 on the 5641R. I then captured the FM demodulated output of the 5641R using the PXI-5661 VSA. What I expected to see was the original 4 fsk signal as it appeared before being passed through the "MT Modulate FM" VI. Instead, I had two tones mirrored around the center frequency of capture.
-Tim S.
03-23-2010 01:57 PM
Hi Tim,
I believe the reason you are seeing the double side band signal is because you are passing a real signal through the DAC in quadrature mode . My suggestion is to downconvert the signal before you pass it to the DAC. An easy way to test your code would be to DMA to the host after the FM demod vi at which point you will have access to this signal and can use the down convert MT vi then pass back to the FPGA to send the down converted signal to the DAC. This will allow us to see the signal you are trying to pass to the DAC as well as use MT and graphs so that we can see what is happening. If this confirms my theory we can then work on downconverting in the FGPA. I am also curious about your generation side. I assume there is an upconvert between the 4FSK signal and the MT Modulate FM as the FSK vi outputs a complex signal and the FM mod accepts a real signal, this is just a guess, so if you could post a screen shot or your code this would be a big help in knowing what we are working with.
03-24-2010 02:55 PM
Hi Jace,
I wasn't able to get working what I wanted to with the FPGA to Host and MT Downconvert VI but hopefully this picture sheds a little more light.
In the first part of the picture, that is what I have at the output of the FM demodulation block when looking at it on a spectrum analyzer (of course the Fc is whatever I set the 5641R's DUC/DAC to and not 0 Hz). Before I write the data to the DAC in FPGA code I believe that the missing steps I need to perform are what I've shown in the 2nd and 3rd parts of the picture. I'm a complete newbie to fixed point math so I'm kind of staring at the fact of doing a hilbert FIR filter & frequency translation and getting baffled. Any advice on how to perform those would be appreciated.
Thanks,
Tim S.
03-25-2010 01:15 PM
Hi Tim,
I think we are pretty much on the same page, I however, no not believe it is necessary to perform a transform but rather just downconvert the signal. Something like the image below should provide what you need to send to the DAC:
You can make use of the sine wave express vi found in the following location:
Below are some links that I hope will help you to further understand fixed point math and hopefully make the transition easier for you. Please feel free to let me know if there is anything else I can help with.
DDS in FPGA
http://zone.ni.com/devzone/cda/epd/p/id/6066
IP net FPGA function reference
http://zone.ni.com/devzone/cda/tut/p/id/4799#toc1
Fixed Point Math overview:
http://zone.ni.com/devzone/cda/pub/p/id/303
Fixed Point Math Library:
http://zone.ni.com/devzone/cda/tut/p/id/7781
03-25-2010 01:45 PM
03-25-2010 02:35 PM
Don't worry, all of the information provided in your one post was extremely helpful in expanding my knowledge of what can be performed on the FPGA and how for some of them. But yes, I was trying to figure out how to apply what you mentioned to what I need to do. I'll try to give a little better example with numbers:
Let's say I had an FM audio signal (0-20kHz frequency content) coming into the "FM Demodulator" vi that's part of the rf communications IP library. The output of the "FM Demodulator" vi would be the original audio signal with frequency content from 0-20kHz when looking at a one-sided power spectrum of it. What I'm currently doing is writing that (real data only) audio signal to the D/A when it's configured in quadrature generation mode and the DUC is outputing that signal at (let's say) 25 MHz. When I put a spectrum analyzer at 25 MHz what I see is the audio signal mirrored around 25 MHz but I believe its cut off to +/- 10kHz around 25 MHz. What I really want is to have 25 MHz be the center of the audio signal so that low frequency audio content is at 25MHz-10kHz and high frequency audio content appears at 25MHz+10kHz. Hopefully this diagram is a little more helpful than my last.
Regards,
Tim S.
03-30-2010 01:26 PM
Hi Tim,
Thank you for the clarification, you were correct in that to achieve what you have described you will need to perform a Hilbert transform. In order to accomplish this in the FPGA you can use an FIR filter to perform the operation adjusting the taps to approximate the Hilbert transform response. IP for an FIR filter is available on IP net the link for which I provided in a previous post, this will require Digital Filter design toolset which I am unsure if you have. Another option is to use the NI IP Integration node and Xilinx core gen to generate a FIR filter with the correct coefficients. More information can be found here http://zone.ni.com/devzone/cda/tut/p/id/10015.
03-31-2010 08:12 AM
Hi JaceD,
After talking with someone on my end who is more knowledgeable in the DSP realm about which filter I should use I decided to use a multirate halfband filter. After browsing around some of the examples I found the one that generates FPGA code from designed filter coefficients and modified it to use a halfband filter. Unfortunately, I discovered that the maximum sample rate I could achieve with a decent quality filter was around 2 MHz. This was dependant on the number of taps in the filter as I found out after reading the autogenerated filter description when it says that it would take 23 cycles to process one sample. It would appear that the autogenerated filter code does not utilize pipelining when convolving an input sample with every tap of the filter. Has there ever been work done to increase the throughput of the FPGA FIR filters so that they pipeline the convolution of taps with samples?
I'm looking to get atleast a 12.5 MS/s IQ rate but it currently doesn't look like that is possible unless I can find the time to do some really advanced FPGA programming which, of course, I'm short on right now...
-Tim S.