08-31-2009 01:07 PM
I'm a grad student at the University of Illinois, and I am trying to get both DACs and both ADCs for the 5640R in sync to do some testing on a single sideband mixer. I already have the ADCs working in sync thanks to the post at:
but I cannot find any information on how to sync up the DACs correctly. Both DACs will output data correctly on their own (i.e. the I/Q data for DAC0 is good, and the I/Q data for DAC1 is good), but every time I run the VI, I seem to get a random phase offset between the two DACs (Shown in the images below).
For the attached images, I hooked the output of DAC0 to ADC0, and the output of DAC1 to ADC1. Then I put a single tone out on each DAC (The data fed into each DAC FIFO is synchronized). The graphs show the I-Channel of ADC0 vs the I-Channel of ADC1. Because the ADCs are synchronized, if the DACs were correctly synchronized I would get a straight line along the x=y axis. However, every time I run the VI, I get a different oval in the Chan0 vs Chan1 graphs shown, indicating a different phase offset. If anybody could provide some insight as to how I can sync up the DACs, that would be very helpful!
I've attached the project in the zip file. Please disregard the OFDM code - to do testing, I'm using some known OFDM symbols read from a file as inputs to my chip, and the ADC outputs will be spit out to a file and post-processed.
09-09-2009 04:05 PM - edited 09-09-2009 04:06 PM
I apologize for the delayed response to this issue, but I believe I have a usable work around for you. I have looked at your code and made some modifications which have shown improvement in the synchronization on my machine. As you can see I have rearranged some of the config vis but more importantly pulsed the config DAC simultaneous reset for one second. Secondly I have done a manual toggle of the DAC profile to ensure that the profile is being changed, as well as removed the DAC reset that you had in your VI.
Please let me know if anything is unclear
09-13-2009 04:34 PM
I’ve tried everything you suggested, but I still get a random phase offset between the two DACs. Could you please look at my HOST vi and see if I’ve done anything stupid? Also, could you please explain how the DAC profiles work? The NI5640R help says that “The active profile is one of the four possible profiles (set of frequency/phase registers) on the AD 9857 that is currently active.” Does this refer to I/Q or single tone operation, or something else?
I have included two screenshots again, showing random phase offsets in the Chan0 vs Chan1 graph.
09-28-2009 01:58 PM
I apologize that it has taken so long to reply once again but I have been attempting to find a work around for you to this issue. I do see the same behavior that you are seeing and I have filed a corrective action request to R&D. I believe we have narrowed the problem area down but we are still looking into the root cause of this behavior. In the mean time I have had limited success manually toggling the dac profile on each run. I know that I have suggested this to you previously and it did not work but it seems that if you change the value between runs there is a greater chance for success. Once again I do apologize that you are running into this and assure you we are working toward a solution, I will post back when it is found.
02-15-2010 10:50 AM
I just wanted to update you on the progress of this issue. We have recently released 5640R 1.4 which corrects the issues found in previous versions and allows the user to synchronize the DACs more closely. Our testing as shown that the DACs can now be synchronized to within one clock cycle so that is 5ns when running at full rate. I hope this helps.
01-31-2012 10:26 AM
Thank you for posting on the IF-RIO forum. This this is an old thread and a bit of a different issue, so I would encourage you to start a new thread for any new questions you may have.
This question is addressed in a previous post - Synchronous upconversion and downconversion using NI PXIe 5641R, and I will repost the answer here.
The VCOs in the ADCs and the DACs are completely separate on the two devices. Synchronizing the DACs with the ADCs at a local oscillator level is not officially supported. The ADCs and DACs are fed the same sample clock, so you might be able to achieve some level of synchronization. However, sub-sample synchronized VCOs between the DACs and ADCs is not likely. You can look at the clock circuitry diagram in the installed NI IF Tranceivers Help >>Devices>>NI PXIe-5641R>>Clocking page. The NI-5640R software gives you control functionality into the ADC and DAC chips directly when using LabVIEW FPGA to program the device. You could look at the datasheets for the ADCs and DACs to potentially get some ideas for synchronizing the ADCs with the DACs.
The datasheets for the AD 6654 ADC and AD 9857 DAC are available from the www.analog.com™ Web site.
I will add that because the IF-RIO has a user programmable FPGA, you may be able to implement some level of synchronization on the FPGA, but it have not been developed or is it supported.
Why do you wish to synchronize the ADCs with the DACs? What is your application? In many RF type applications the reciever and transmitter are not able to be phase matched so demodulation schemes take this into account.
02-02-2012 09:24 AM
Thank you for your answer. Actualy it was me that started the thread: Synchronous upconversion and downconversion using NI PXIe 5641R.
I just wanted to know if someone could provide an hint about synchronising the ADCs with the DACs.
I am in interested in standard control application: I need to regulate the amplitude and the phase at the output of a RF amplifier.
I would be hard to explain the details here, so I will use a simple example instead.
Suppose that I want to measure the electrical length of a cable (i.e. the phase shift caused by the cable).
I could do that by:
- Generating aconstant I-Q signal and upconvert it using an DAC (say DAC0);
- Connecting DAC0 with ADC0;
- Reading the I-Q signal from the ADC0;
- Measuring the phase difference between between the generated IQ signal and the one read from DAC0.
Of course this is possible only if ADC0 and DAC0 are synchronised. And, as far as I know, I cannot do that.