04-09-2012 03:28 PM
I am using LV7.1, NI-Scope. I have 3 PCI-5105 cards. I am running an external clock into PF1 of each card, with identical length cables. I am using 1 analog channel (channel 0, dev1) to trigger aquisition on the remaining 23. The system runs well at 30MHz and 40MHz, but when I choose non native sample rates for the 5105 (24Mhz as an example), the second and third board don't receive and begin data aquisition until some number of samples after the first board. The base of my program is the "niScope EX Multi-Device External Clocking (TClk).vi" where I use the Tclk vi's to synchronize data aquisition. In reading the 5105 specifications I notice the reference clock is 10Mhz. To get sychronized triggers must I run at a multiple of this frequency or is there some other issue I may be missing?
Thanks for any help,
04-10-2012 12:52 PM
I see you're using the PCI-5105 digitizers. You mentioned that you were using an external clock to each card with identical lines. This is correct for how to do that type of clocking. You also indicated that you wanted to use one channel to trigger the remaining 23. I took this to mean the 7 other channels on this card, and 8 channels on card 2 and card 3 for a total of 23. If this is incorrect, please let me know.
I pulled up the specifications manual for this device to look at it and found the sample clock (page 10). It looks like this device's sample rate rage is 60 MS/s and to get rates less than this, the divide by n decimation method must be used. This is why you're getting good behavior with values like 20 and 30 MHz. 40MHz is not a divide by N, but it is a 1.5, so you're still getting acceptable behavior.
The NI High Speed Digitizers help has a section on the Sample Clock. This section talks a bit more about the decimation method Basically the ADC still samples with the onboard clock. Then it sends the data to the decimator which pulls off every N sample to get to the sample rate. I believe this is the same sort of behavior with the decimated external sample clock.
To generate TClk signals, devices must have a common reference clock or sample clock/timebase. Check out the NI-TClk overview for some more information on this. TClk does work with internal and external sample clocks as long as all of the sessions synchonized together (in your case, the three cards. Check this out for TClk with external sample clocks.
Please let me know how else I can help!
04-10-2012 01:31 PM
Hi Lea D,
Thanks for responding to me. You are correct, I am using the 7 remaining channels on card 1, and the 8 channels on card 2 and 8 on card 3 for a total of 23. I am reading all the links you gave me and I will try the ideas and get back to you.
04-10-2012 01:34 PM
I know there's alot of information there. I'll keep you posted if I think of anything else as well.
04-12-2012 11:36 AM - edited 04-12-2012 11:37 AM
I think the first post that I had was pretty irrelevant since you're not using decimation in your application and just using the external sample clock. Sorry about that.
You mentioned using the niScope EX Multi-Device External Clocking (TClk).vi as the base for your program. Can you post the modified code? Also, does this syncrhonization accross boards work with the example completely unmodified with different frequencies (multiples and non-multiples of 10MHz). I'd like to work off of the unmodified example first so that we can rule out any problems with the hardware itself then we can pinpoint exactly what is causing the problem if it's in the code.
If all of the devices are configured to read from this external clock and their all the same length, then frequencies between 8 to 65 MHz should work. Are all of your devices configured to read from this PFI line? When sample rates are different accross devices but multiples of the 10MHz reference clock, the instruments all have sample clocks that are synchronous to eachother. When they aren't integer values, there's no guarantee that the clocks are in phase. Check out the section called "Sample Clock Synchronization" at this link.
Please let me know about the unmodified example, and I'll try to find some hardware to hook this up and test with. It would be helpful to have a screencapture of your front panel so that I can make sure all of my settings are the same as yours.
04-12-2012 12:45 PM
Thank you for looking into this further. I will need to set up the scope again and pulse generators, then I will send you what you ask for.
All 3 boards are configured to use PF1 as their external clock source and this clock is coming from 1 pulse generator. I will use the unmodified code at first, then the modified. Will this posted code be available to anyone reading this blog?
04-12-2012 01:07 PM
It will be available to anyone reading this because of the nature of our forums. Do you have a support with National Instruments? If so, you can open a request at ni.com/support and specifically reference this discussion forum and we can take this issue off the forums.
That beign said, I don't think posting would be entirely necessary since I won't be able to fully debug code. If the example works fine, try adding in things one by one to get the code back to the original modified state so that only one variable changes at a time. This will narrow down what addition is causing the problems and we can look into why that specific addition is causing misbehavior.
04-12-2012 01:35 PM
Attached is the modified ni scope example. With saved as default front panel settings. The only modification was making a loop into the data acquisition portion so it runs continuously. I save the out of sync waveform at 24Mhz in the front panel waveform graph. I ran this at many different frequencies and I agree with you that the out of sync behavior is on non 10Mhz steps, but on some of the non 10Mhz steps: 45Mhz as an example, it will run in sync and occasionally it will run in sync at 24Mhz.
04-12-2012 01:57 PM
Were you able to try the unmodified example to verify correct behavior? I noticed with the while loop that it's around all of the configure and initiation steps. So each time it goes to fetch those clusters over and over again, it's also configuring the trigger, setting up; the sync, and reinitiating each time a fetch goes into it. Also the first call into the syncronize thing might be throwing it off.
This external clock you said was from a pulse generator, what kind of pulse generator is this (make/model). Is it completely separate from the system? I'm working with one of our arbitrary waveform generators making a square wave. Check out page 13 of the specs manual for information ont he ranges of this. I believe your pulse generator would be like a square wave, so be sure that the peak to peak value is between .2 and 2.8 Volts.
As a sidenote... the behavior that you're seeing does sound alot like what I was saying earlier:
When sample rates are different accross devices but multiples of the 10MHz reference clock, the instruments all have sample clocks that are synchronous to eachother. When they aren't integer values, there's no guarantee that the clocks are in phase. Check out the section called "Sample Clock Synchronization" atthis link.
It doesn't look like your set up with this, but it's odd how similar of behavior you're getting. Please let me know about the unmodified example.
04-12-2012 02:42 PM
Attached is the unmodified version with saved waveform and front panel settings at 24Mhz. The waveforms are out of phase.
I am using an HP8116A 50Mhz Pulse/Function Generator, clock signal is 2.5v pk-pk with baseline at 0v
I made myself a new version without any of the Tclk subvi's inside the while loop, it would only execute one time with new data.
I then put the Tclk subvi inside and it ran continuously, although this did not improve the phase problem at rates not multiples of 10Mhz.
Okay I have read all of the links you have supplied and I believe we need to run at multiples of 10Mhz. Thanks for your help.