Hi,
I want to PLL my 5761 to PXI_CLK10 by setting the Sample Clock Select signal. I'm using the adapter with a PXIe-7965.
The 5761 manual Clocking section leads me to believe I can do this: "Reference Clock, 10 MHz, External through IoModSyncClock".
The 5761 Multiple Sample CLIP topic in the FlexRIO Help gives me the value to write, "Sample Clock Select, 3 = Internal Sample Clock locked to an external Reference Clock through IoModSyncClock".
And <labview>\examples\FlexRIO\IO Modules\NI 5761\NI 5761 Clock Select\NI 5761 - Clock Select.lvproj shows me how to set the clock source to "Internal Clock PLL On (IoModSyncClk)".
I'm missing how to route PXI_CLK10 to IoModSyncClock.
There's an explicit note in Table 4 of the 5782 manual that states, "The internal VCO locks to PXI_CLK10 through IoModSyncClock, which is available only through the backplane of NI PXIe-796xR devices", when the clock is set to Internal Clock PLL On (IoModSyncClock). Perhaps the same applies to the 5761 even though they seem to have different clocking options?
I don't want to cable the CLK10_OUT from the chassis to CLK IN on the 5761 (that seems silly). I don't want to use the FlexRIO Instrument Development Library Sync API to PLL to the backplane.
Thanks for any help,
Steve K
