NI 5171R Reconfigurable Oscilloscope: External clock frequency range

[fabrizio_giorgetta]

[Re-posted to correct forum]

Hi,

I am trying to port a LV FPGA project originally implemented for a NI 7965 (fpga) & 5761 (digitizer) combo to a 5171R. The project acquires data on one channel using an external clock at either 200 MS/s or 100 MS/s sample rate given by an external clock.

Looking at the 5171 sample projects (stream data / multi-channel acquisition) for the reconfigurable oscilloscopes, I found some clock configuration VIs. In those, the (user provided) external clock rate is compared against device capabilities -> max,min ext. clock rate. Both those values are hardcoded to 250 MHz.

Does this mean that the external clock has to be 250 MHz for the 5171R? I could not find any external clock frequency range on the spec sheets for the 5171R

The 5761 has different clips supporting <150 MHz clocks (low speed clip) and 'standard' clocks (175 MHz to 250 MHz according to spec sheet).

Thanks,

Fabrizio

[Nathan-P]

"Does this mean that the external clock has to be 250 MHz for the 5171R?"

Yes, the internal sample clock rate is 250MHz, and the only acceptable external sample clock rate is also 250MHz.  This is defined in the spec sheet on page 15 and 16: http://www.ni.com/pdf/manuals/374273a.pdf

This is one of the differences between the NI 5761 FAM and the PXIe-5171R reconfigurable oscilloscope.  

-Nathan

[bcl511]

Hi Nathan,

I'm also using the 5171r and I have a related question about this.  If you look at the block diagram on the datasheet, page 3 (http://www.ni.com/datasheet/pdf/en/ds-548) it would appear that there is a path to send a 10MHz clock into the onboard PLL, either from the PXI backplane or from the clock in input, and have it converted to the 250MHz ADC clock.  Is there no way to provide a 10MHz external clock as the reference for the sample clock?  If so then the block diagram is a bit misleading.  

thanks,

Ben

[Nathan-P]

HI bcl511,

The discussion on this thread was about an external sample clock, which is required to be 250MHz.  The onboard VCXO can be PLL'ed to an external reference clock (10 MHz).  

I believe this is the diagram you are referring to?

In this diagram, it shows that the source of the "external sample clock" can be from CLK IN, or from PXIe_DstarA (from a timing and sync module).  The device requirement is that this external sample clock frequency be 250MHz.  

The other path is through the phase locked loop, and this selects reference clock sources.  The diagram above correctly shows that the source for this signal is CLK IN or the PXIe_Clk10 signals.  The requirement for the reference clock is that it's frequency must be 10MHz.  (page 15 of specifications)

Therefore: You are right, you can use a 10MHz clock as a Reference Clock but this will not change the frequency at which the ADC will be sampling.  

For more information regarding the difference between a sample clock and a reference clock, I reccomend these from the Fundamentals section of the help file: High Speed Digitizers Help File >> Fundamentals >> Clocking

(http://zone.ni.com/reference/en-XX/help/370592Y-01/TOC14.htm)

Specifications document:

http://www.ni.com/pdf/manuals/374273a.pdf

[Frederic.iov]

Hi,

I have the same trouble, it seems that it is not possible to route the external clock toward the data clock.

I can't find how to say to the FPGA to take the external CLK IN from the AUX I/O in order to derive the Data Clock...

The theroretical diagram is useless since the option to make the clock selection apears nowhere in LabView.

If anyone have an idea ?

--
Florent

[bcl511]

Hello Florent,

I had the same confusion at first.  The clock control does not in fact appear anywhere in the FPGA part of the code but you can get to it from the host side.  If you start from the stream-to-host template and descend through the subVIs as follows, you will see it:

Device Session.lvclass: Open Session.vi  -->  niHSAI Config v1 Host:lvclass:Configure ADC Clock.vi -->   niHSAI Config v1 Host:lvclass:Configure ADC Clock Impl.vi

Alternately you can get to that function through the pallettes as follows:

FPGA Interface --> Software Designed Instruments --> Oscilloscopes --> NI PXIe-5171R --> Configuration --> ADC Clock Config.vi

As far as I've been able to tell the FPGA portion of these scopes is a walled garden of sorts, in that they let us play with the data in the middle but all of the IO is hidden away and is only accessible from the API on the host side.

Cheers,

Benjamin

[balexand]

I would like to point out that the clocking circuitry that Nathan-P posted is not part of the FPGA, but involves other physical parts on the board.  This clocking circuitry is programmed by niHSAI Config v1 Host:lvclass:Configure ADC Clock Impl.vi as Benjamin pointed out.  That VI uses the FIFO Register Bus library to send data down to the LabVIEW FPGA design, which then writes out the commands to the external chips using /instr.lib/HSAI-RIO/Config/Group A/v1/FPGA/Device Registers/Bus Interface.vi

[Frederic.iov]

Many thanks for your answers and NI Support help.

I'm now trying to introduce the clock configuration in the project.

Thanks

--

Florent

[Frederic.iov]

So, at the end of the day, the modification has to be done in the "Open Session.vi" (in the host VI).

The "configure ADC clock" component has to be cabled as in the Device Session resources folder, file Configure External Clock.vi

 

It is working well.

Thanks

--

Florent