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How to delay a trigger with PXI-5122 before routed to PFI line

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Yes, when using a reference trigger, the trigger timestamp uses the trigger event at time 0.  Thus all pre-trigger samples are negative, and post trigger samples are positive.

Systems Engineer
SISU
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Message 21 of 24
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Hi Nathan,

 

In another setup, the Dev_1 trigger both the digitizer (via TRIG connecter) and the Dev_2 at the same time. You can see the signal (received signal caused by Dev_1) is actually there. (1)

t2.jpg

 

Here is the result of the current setup: (2)

t3.jpg

 

If the Dev_1 only trigger the digitizer, there are no signal. (3)

t4.jpg

 

From the setups (1), (2) and (3), I found out the reason is that the Dev_1 couldn't trigger the digitizer via PFI 0. Follow the help file, the PFI 0/1 are the digital trigger lines, while the trigger from my Dev_1 is analog. So it may be the problem.

I'm trying to find the solution. Please let me know of your suggestions, if you have any.

 

Have a good day!

 

Best regards,

 

John C.

 

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Message 22 of 24
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I find out two ways to solve this problem. The first requires another board followed this topic. The second one is fabrication a mini-circuit to convert the analog trigger signal to digital signal before routed to PFI line.

 

Hope this help!

 

Regards,

 

John C.

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Message 23 of 24
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What does your trigger from dev_1 look like?  In our entire discussion you depicted it as a digital pulse, so if it is not a digitial pulse, what is it?

 

If we have to acquire it as an analog signal, on TRIG, then it can only be a reference (stop) trigger, and we cannot implement your timing and acquisition like that.  

 

Your solution to create a comparator circuit is a good option, and using another board to acquire the post-export-delayed-trigger signal would also work, export a signal to Device_2 and seccond_5122_board .

 

A third option would be to use the PXIe-5170R or PXIe-5171R, which using LabVIEW FPGA, you could acquire the data, and create a delayed signal easily, since the hardware is open for custom implementations on the PFI lines.  

http://sine.ni.com/nips/cds/view/p/lang/en/nid/212657

 

I hope this helps,

Nathan

Systems Engineer
SISU
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Message 24 of 24
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