UDP implementation in FPGA on SOM Dev Kit

[Artavazd]

Hello everybody,

SOM Dev Kit coming with carrying board has two Gigabit ethernet ports. One of them (ETH1) can be accessed from FPGA by CLIP. I'm trying to implement UDP on SOM's FPGA and would like to know Is there any reference example or everything should be done from scratch?

Thanks in advance,

Artavazd

[tannerite]

Hi Artavazd,

EDIT: I didn't see at first-glance you were talking specifically about FPGA IP for interfacing with the Ethernet PHY from the FPGA since it is a pass-through. NI does not have any specific examples for modifying the CLIP to use the FPGA to directly interface with the PHY. This interface is really meant to be used in LabVIEW RT through the Zynq's processor subsystem rather than directly from the FPGA. It was exposed through the FPGA to allow both for optionally enabling the interface and due to the limited pin-count of the Zynq processor subsystem. That is not to say it cannot be used for other purposes; however, we don't have reference VHDL for this.

Is there a reason you need to use the FPGA for UDP traffic rather than through LabVIEW RT which provides the full network stack?

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The sbRIO-9651 SOM's Gigabit Ethernet interfaces behave just as any other Ethernet interface in LabVIEW or LabVIEW RT. You can use the LabVIEW UDP VIs to communicate with either port on the SOM. 

I recommend opening LabVIEW and selecting Help → Find Examples. Once the NI Example Finder opens, then navigate to Networking → TCP & UDP. There are several UDP-specific examples to get you started. Since the SOM Carrier Board has two Ethernet interfaces, you can specify in the UDP VIs which network interface by specifying the net address input on UDP Open VI.

-Tanner

[Artavazd]

Hello Tanner, Thanks for your response!

I have experience of using both ethernet ports in SOM Dev Kit from linux RT. However, there is a research project in which the UDP traffic implementation on SOM's FPGA is required. As I understand the hardware layer (SOM + Dev Kit) is fully capable for this kind of implementation. Taking into consideration that NI has the UDP implementation for High Seed Serial Instruments, I guess that only MAC layer should be changed under SOM FPGA.
And one more quistion: What kind of FPGA package is used in zynq 7020(which used in SOM)?

With best regards,
Artavazd

[Spex]

Hi Artavazd,

The MAC implementation on the Zynq and hence SOM is a hard IP in the Zynq PS.  The FPGA is routing the PS MAC to FPGA pins and applying timing constraints (Xilinx refers this as eMIO).  

Implementing UDP communication directly from the FPGA would require a soft MAC IP and associated UDP network IP. NI does have a UDP implementation for High-Speed Serial instruments and the Controller for FlexRIO, but honestly I'm not familiar enough with those implementation to predict the caveats of trying to migrate them to SOM.  

For example, the SOM used a GMII PHY interface because we had trouble consistently meeting the timing requirements of RGMII though the fabric. I don't know if the NI UDP IP is fixed to GMII, RGMII, or is flexible.  The High-Speed Serial and FlexRIO products both use higher end FPGAs (Kintex 7) which are capable of higher speed signaling.

Our guidance at this point is you would be working from scratch on getting UDP working from the FPGA on SOM.  The IP from High-Speed Serial Instruments may be a good starting point, but I'm not aware of anyone attempting to use on Zynq.  

Lastly, as a point of information, if you implement the MAC in the FPGA, then the limit to the number of ports you could support is the logic in the FPGA and the number of availble IO pins.  The two port limit on the SOM and the CLIP generator is set by the number of hard IP MACs in the Zynq processor.

Regards,

[Artavazd]

Hi Spex,

Thank you for detailed explanation and advises. We have started the development on Zynq's FPGA from scratch using open source MAC wrappers written in VHDL for GMII.

Best regards,

Artavazd

[MrJackHamilton]

Artavazd,

I am familiar with employing TCP/IP and UDP on NI RT, cRIO and embedded systems.

I'm scratching my head as to why you'd want to consider employing UDP on the FPGA, it's not the circuit per se that is the issue IMO, it's the massive and complex memory and logic to handle the TCP/IP interface logic. Even the most basic implemention requires a memory buffer, which FPGA's don't have inately, but can be emulated via shift-registers.

You might be using the RT via a FIFO to handle the memory needs, as the SOM FPGA does not provide for direct access of the DMA on the SOM [Unless something has changed lately].

I'd be interested to hear the resutls of your effort.

BTY: The last time -1 yr ago I tried UDP on a cRIO RT system - it did not work, and was not implemented by NI. At that time, my discovery took them by superise.

[nturley]

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You might be using the RT via a FIFO to handle the memory needs, as the SOM FPGA does not provide for direct access of the DMA on the SOM [Unless something has changed lately].

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FYI, Something has changed lately. Host Memory Buffer gives you random access to a block of host memory. Might simplify something like this.

--Neil