UART Baud rate Question?

[MOONANI]

Hi~!

Well, I think this bbs is only one place I can ask about my problem.

I'm working with NI-9651. My system needs to communiucation with IMU deivce with serial(RS-232) comm.

Communication with IMU though 115200 bps (100byte data per 20ms) has no problem. however, my client request speed up serial communication.

100byte communication with 1Khz period.

IMU Support  1KHz periodic communcation with 1000000bps. the problem is SOM. It support upto 230400 bps.

Without buad rate chagne, It's seems like difficult.

I think I have a three option.

One, add UART IP (can support 1Mbps) to SOM and re-route conventional pin.

- I think converntional FPGA IP could support 1Mbps communication. So... I think this solution is hopeful!

Two, Using USB communication.

- I follow some USB related questions, the problem is USB is identifiec as network card. . I check USB driver and confirm RT Linux has already my usb-serial cable driver.

.so..Maybe I need to make USB driver...

Three, Quit the job.

- Happy. and hungry.

I just want to know Your OPINIONs .

Thanks!!

[Deagle]

Moonani,

I would recommend the UART IP option. You could integrate a VHDL core into your design, or create one using LabVIEW. Here's a LabVIEW FPGA UART example that seems well documented. It may take some work to migrate this code to Single-Board RIO though.

Thanks,

Bryan

[MrJackHamilton]

I've done this: Implemented a UART in the SOM from the existing NI FPGA UART example code.

You will need to update the following:

1. Update the FPGA Pin Assignments to your SOM assigned Pins.

2. Update the FIFO between the FPGA and RT.

That said: The original implementation of transmitting the Serial Chars between the FPGA and the RT was a boolean interrupt and a 'screen-scrape' from the FPGA front panel char indicator to the RT. I am not sure exactly how fast this is, it would be limited by the RT, further, as you implement more code on the RT, this speed will be affected.

I would implement a FIFO to transmit the FPGA read serial Chars to the RT. (The FPGA only reads one character at-a-time) and the RT concantentates the chars into the serial message 'words'.

When using a FIFO on the RT, take some time to balance the timing of the RT read loop. The 'FIFO Read' function does not seem to implement as an interrupt, so if you don't set the loop timeout correctly, it will chew-up lots of RT processing.

Regards

Jack Hamilton