Need help with dma fifo in fpga, sensor initialization and some more stuff

[GoKu25]

Hi Folks,

The scenario is, I have a sbRIO 9651 and a MPU 6050 (A IMU sensor). I would like to acquire sensor data in FPGA VI, stream it to RT VI for processing and analysis and view it from windows based VI. I came across certain problems which I wasn't able to figure out. I dont have the appropriate cable to interface the sensor yet, which I have ordered, to test the VI.

1. FPGA VI:  The I2C Master VI outputs a array of 14 bytes raw data (6 bytes for Accelerometer, 6 bytes for gyroscope and 2 bytes for temperature). since the data can only be written element by element in a DMA FIFO, how can I stream an array to RT VI. I did an auto-indexed for loop to write data and I dont know if this will work.

2. RT VI: Initialization of MPU6050 is done here. It involves writing a byte array sequence to I2C Master VI to configure it and then a write-read(writing a register to read data from) process to acquire data. I am not sure how to do the write- read part.

3.  The single process shared variable 'RT Stop' used for communication between loops in RT VI is written a value after the loop ends which I dont know as to why. The architecture is based on the Turbine example from cRIO developers guide.

I am attaching the VIs for your reference. Please have a look into the code and let me know if you find anything that needs correction. I am totally new to Real time and FPGA programming.

Update: Added a previous version- 2013 of the VIs

Thanks a ton

Gokul

Message was edited by: GoKu25

[MrJackHamilton]

Gokul,

Welcome to the world of FPGA and RT!. A couple of thoughts/things...

1. FIFO: You cannot send 'arrays' what you can do is send one 'element' of data at a time. This is how the FIFO works. The FPGA can stream data into the FIFO quite well. The work you need to do is tune the RT side to receive the FIFO elements and build the array on the RT side. It's not commonly discussed by NI that you need to tune loop timing on the RT side. This in my opinion is from a short coming in the RT FIFO read implementation. The RT FIFO read does NOT create an interrupt, as, for example the DAQmx Read function.

No.1: You need to drop the VI server node for the RT that reports the CPU load. I don't know why this feature is not more discussed, but it's the gauge by which you will tune the RT, because reading the FIFO loads the RT CPU, you can't open the FIFO read full-throttle , it will max out the RT CPU and it will drop elements resulting in lost elements in the FIFO.

What I mean by 'tuning' is you have to balance the FIFO total buffer size (set it to max), on the RT size, set the read buffer size to something like 256 on the initialization of the FIFO read loop. Inside the FIFO read loop set the read size to 128, (this assures it does not catch up with the total buffer).

Also, on the RT the FIFO read, MUST run in its own loop. I don't recomment do anything else in that loop, unless your data processing is very light. Employ Queues to pass data segements out of the FIFO read loop to another 'processing' loop.

Taking the time to understand the FIFO system in the RT is a very important first step.

Regards

Jack Hamilton