BANK 3 Voltage IO

[lucamonopoli]

Hi ,

i'd like to change voltage reference on bank 3 from 3.3volt to 1.8 volt.

i'm using the carrier board and so i have a switch to select power supply to the bank.

Is there a procedure in order to change voltage bank supply,without damaging io's, before or after fpga bitdown stream ?

[tannerite]

Hi lucamonopoli,

The guidance is not to drive the I/O bank voltage with a higher voltage than what is configured in the bitfile (set in the sbRIO CLIP Generator). There are two scenarios to consider:

1. The bank voltage and bitfile is configured for a higher voltage, say 3.3V, and you wish to use a lower voltage, say 2.5V. It is advised to first change the I/O bank voltage, then change the pin constraints in the sbRIO CLIP Generator to be a 2.5V signal standard.
2. The bank voltage and bitfile is configured for a low voltage, say 1.8V, and you wish to use a higher voltage, say 2.5V. It is advised to first change the pin constraints in the sbRIO CLIP generator, recompile the bitfile and deploy before changing the Bank 3 jumper to 2.5 V. 

The above scenarios ensure that the bank voltage isn't higher than the I/O standard that was previously selected. Xilinx states in the Series 7 Select I/O Resource document the banks enter an over-voltage protection mode if Vcco (bank voltage) exceeds the I/O standard in the pin constraint; however, the above guidance still applies to prevent encountering this scenario. Please let me know if you have any additional questions around this topic.

EDIT: The above can likely be explained more concisely as follows: Vcco bank voltage should be less than or equal to the pin constraints (defined in the sbRIO CLIP Generator) at any given time.

-Tanner

[lucamonopoli]

thanks a lot 

LM