Example Programs

cancel
Showing results for 
Search instead for 
Did you mean: 

Passing, Converting, and Graphing Analog Data Through a U32 FPGA FIFO

Overview

This example demonstrates how to combine two I16 values to send them most efficiently from target to host using a DMA FIFO with U32 datatype. For demonstration purposes signal values are generated by a sine wave generator on the FPGA.

 

Description

In earlier versions of LabVIEW, the FPGA FIFO is fixed at a U32 Datatype. Since LabVIEW 8.6 any standard type can be used, including fixed point (Release Notes).Also in newer LabVIEW versions the DMA FIFO interface between FPGA and DMA buffer is 32-bits wide. Thus it is most efficient to package 16-bit numbers into a single 32-bit value, and then unpack it on the host. When using a U32 FIFO, it can be confusing when your I16 data gets coerced to a U32 and then Read as a U32 on the host, which requires some careful data conversions. This example shows a way to pack two I16 values into a U32 and then to unpack and continuously show the data on a waveform chart.

This example was built for a cRIO 9118, but can be applied to many different FPGA targets.


Requirements

 Software

  • LabVIEW Full oder Professional Development System 2012 (or compatible)
  • LabVIEW FPGA Module 2012 (or compatible)
  • If running in a Real-Time context, you will need the LabVIEW Real-Time Module 2012 (or compatible)

 Hardware

  • FPGA target (e.g. cRIO 9118 or compatible)

 

Steps to Implement or Execute Code

  1. Download and open the attached file "Pass two I16 through U32 DMA FIFO LV2012 NIVerified.zip"
  2. Follow the instructions in Front Panel of "Host receiver.vi" and "FPGA sender.vi" and run the program

 

Additional Information or References

Host receiver:

Frontpanel.png

 

Host receiver.vi - Block Diagram.png

 

FPGA sender:

FPGA sender.vi - Front Panel.png

 

FPGA sender.vi - Block Diagram.png

 

Note: You can modify the chart history length by right clicking on the waveform chart. Also be sure to change the desired loop rate in "Host receiver.vi" to be representative of the rate you are reading on the FPGA. For this example, I was generating data at 1 kHz on my FPGA which has a top level clock of 40 MHz, so I chose 40k ticks as a desired loop rate. If you have another FPGA target, you might have to consider its different top level clock and change ticks for desired loop rate accordingly.

 

Find more detailed examples about this topic under:

<LabVIEW 201x>\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\Generation

 

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

Rob K
Measurements Mechanical Engineer (C-Series, USB X-Series)
National Instruments
CompactRIO Developers Guide
CompactRIO Out of the Box Video
Comments
Active Participant Robbob
Active Participant

Please leave feedback if you have any comments or suggestions!

Rob K
Measurements Mechanical Engineer (C-Series, USB X-Series)
National Instruments
CompactRIO Developers Guide
CompactRIO Out of the Box Video
Member SpaceHunter
Member

add the version numner into the file name

Active Participant Robbob
Active Participant

Good call. Original files were for LV 8.6, but this example helps 8.5 users more. I'll convert the files and upload them later today!

Rob K
Measurements Mechanical Engineer (C-Series, USB X-Series)
National Instruments
CompactRIO Developers Guide
CompactRIO Out of the Box Video
Member soljiang
Member

Thanks Robbob.  I do need the 8.5 version because I cannot open these file.  Looking forward to the new files.

Best,

soljiang