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Overview
The example demonstrates benchmarks of the CPU load when using different methods of DMA FIFO communication.
Description
DMA FIFOs are an efficient method for streaming data from and to an FPGA. DMA stands for Direct Memory Access and DMA FIFOs are able to read/write data directly from/to the Real-Time's memory without causing too much load for the CPU.
In case the DMA FIFO transfers data from the FPGA to the Real-Time system, the data placed in the memory has to be read by the Real-Time application from the memory. For this operations there are several techniques to perform that tasks that differ in CPU load and whether the technique returns a fixed number of elements or a variable number of elements.
Requirements
Software
Hardware
Steps to Implement or Execute Code
Additional Information or References
The test was performed with a CompactRIO-9076 and LabVIEW 2012 and NI-CompactRIO 13.0:
Method | CPU Usage (%) |
---|---|
Blocking | 96 |
Polling | 19 |
Polling with Fixed Elements | 92 |
IRQ | 17 |
Poll for Size | 11 |
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Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
That would be great if U downcast it to LV09! Thank you!
really helpful, cheers