Synchronize 4461 and FPGA

[nickstorton]

Hi All,

I'm trying to evaluate the performance of a new ADC we are designing and need to measure the noise performance across all code values. I have a PXI-4461 to generate all of the step levels and am acquiring the ADC digital data using an FPGA. I know exactly how many samples I need to acquire for each level and how many samples to ignore at the front and back of each level (to stay away from the rising edge of the stair), I also know the precise sample rate of the DSA. As I understand it the FPGA is phase locked to the PXI_CLK10 in the hardware and this cannot be changed. I have set the 4461 Refclk to be PXI_CLK10 and I issue a sync pulse from the FPGA to start the DSA generation. My thinking is that because these two devices are now phase locked to the PXI_CLK10 clock and the FPGA "knows" when the DSA started generating it's signal I should be able to acquire an exact number of samples from my ADC using the FPGA and then pass the relevant samples back to my windows host for analysis. The problem I have is that it appears that the FPGA and DSA are not, in fact, phase locked as, over time, I see that the acquisition window is moving. I modified my FPGA code to output a pulse when I start acquiring each segment of samples and sure enough I can see it moving,"sliding", with respect to the DSA output. As the FPGA is hard wired to be phase locked to the backplane clock I'm guessing that the problem must lie with the DSA not being phase locked to the backplane but I cannot figure out why. Anyone got any ideas?

Thanks all,

Nick