Register Level DMA programming for NI6533

[saxman]

I am writing a register level driver (LynxOS) for the NI6533. I have the DAQ DIO register map (http://www.ni.com/pdf/daq/us/release_ni6533.pdf) but it does not list registers for the DMA controller chip.

Is there a manual that describes how to setup the DMA registers for this board?

Thanks,
- Larry

[Christian_L]

Hello Larry,

Make sure you have all the files and examples included in the MH DKK for the 6533.

http://sine.ni.com/apps/we/nioc.vp?cid=11737〈=US

The examples include two DMA examples that show the use of the necessary registers on the MITE chip which is the PCI interface and DMA controller. The DMA examples are example 12 and 13.

I have also attached the MITE RLPM which includes the same information.

Christian L
NI Consulting Services

[saxman]

Hi Christian,

Thanks for the MITE RLPM, that was the missing piece.

I am now having trouble getting two NI6533's to handshake. One is in a PCI x86 box running LynxOS, and the other is in a desktop PC. For the latter I'm using the Examples:Harware Input and Output:Traditional DAQ:Digital Input and Output:653x examples from LabView 7. Specifically, the Buffered Handshake Output.vi and Cont Handshake Output.vi.

The Cont Handshake Output vi is timing out at 1 second intervals waiting for the write to complete, so I'm assuming from this that no handshaking is occurring.

I can toggle the data lines statically and that looks OK in both directions. I've set the exchangePins bit=1 to swap the ACK/REQ signals on the LynxOS side.

I've attache
d a file that prints the register settings for all of the DIO registers on the LynxOS side. Perhaps you can spot something that's not right?

Also, I'm confused about the delay register settings. The manual states you can adjust the programmable delay from 0 to 700ns in 100ns increments. Yet all of the delay registers show 8-bits. I assume then that only the lower 3 bits are used.

The examples dio_ex12.cpp and dio_ex13.cpp set the group1ReqDelay=3, group1RegNotDelay=2, group1AclDelay=2, and group1AckNotDelay=2, which are consistent with this assumption. However, they set the group1DataDelay=100, which is not consistent. Is this register different than the others?

Thanks,
- Larry

[saxman]

UPDATE: I now have the NI6533 configured so that it will send an ACK in response to a REQ.

The problem I am having now is that when the NI6533 generates an interrupt, it continuously generates them, even though I clear the CPUINT Enable in the MITE and also clear the group1InterruptControl register (as in dio_ex5.cpp) as well as the MasterInterruptControl.

Is there something else that should be done when an interrupt occurs?