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RLP for Multi-Channel Analog Output on PCI-6071E using FIFO

I am developing a register-level driver for the PCI-6071E bd in "C" running under a proprietary real-time kernel. I have substantial experience with RLP for NI bds.

I want to interleave DAC values in the Analog Output FIFO. That is, the first DAC entry is for DAC0, the 2nd is for DAC1, the 3rd is for DAC0, etc. It is my understanding that this is possible by setting AO_Multiple_Channels to 1 and setting AO_Number_Of_Channels to "1" (indicating that DAC's 0 thru 1 will be used in the multi-channel update). However, despite setting these register bits, every FIFO entry goes to BOTH dacs. That is, on the first UPDATE, both DACs output the first FIFO value. On the 2nd update, both DACs output the 2nd FIF
O value, etc.

I have perused everywhere on the NI web site and have been unable to find any RLP example that shows using the FIFO with interleaved DACs. However, I did notice some questions/answers on the developer forum that suggests that the capability exists and is supported in Lab View. Unfortunately, LabView is not an option in this application.

Is there some other register that is involved in this mode of operation?
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