NI-TIO (1) location in PCI BAR1 for the 6624

[erikg]

I am trying to confirm the offset into BAR1 for the TIO(1) location on the 6624.
The TIO RLP manual lists x0800, but it is only for the 660x cards.
I crash when I try to write to the offset.
Thanks.
-erik

[Malcolm]

The Offest for TIO(1) is indeed 0x800 just like the 6602 and 6608.  From a programming perspective, the 6624 is nearly identical to the 6602.  The only real difference is that the 6624 uses a 20MHz clock instead of an 80MHz clock.

My guess is that the MITE is not correclty initialized.  If you haven't already, you should take a look at the examples in the Measurement Hardware Driver Development Kit (MHDDK).  It already has support for a lot of operating systems.  What OS are you using.

Here is the relevant MITE initialization from one of the MHDDK examples:

//Tell the MITE to link the  BAR1 address to the DAQ Board
//You must initialize the MITE before you write to the rest of the PCI board
void initMite(iBus *bus)
{
 tAddressSpace  Bar0;
 u32 physicalBar1;
 
 //Skip MITE initialization for PCMCIA boards
 //(which do not have a MITE DMA controller)
 if(!bus->get(kIsPciPxiBus,0)) return;
 
 Bar0 = bus->createAddressSpace(kPCI_BAR0);

 //Get the physical address of the DAQ board
 physicalBar1 = bus->get(kBusAddressPhysical,kPCI_BAR1);
 
 // ***** 6602/6608 specific MITE initialization *****
 // Hit the IO Window Base/Size Register 1 (IOWBSR1) in the MITE.  We set the
 // address, enable the window and set the size of the window:
 Bar0.write32(0xC4, (physicalBar1 & 0xffffff00L) | 0x8C);

 // Write to the IO Window Control Register 1 (IOWCR1) to make the IO window
 // go to RAM memory space instead of the config space
 Bar0.write32(0xF4, 0);
 
 // ***** End of 6602/6608 specific code *****
 
 bus->destroyAddressSpace(Bar0);
}

[erikg]

Malcolm-
Thanks for your help!  It crashes farther down -

void CounterIO::initTIO6624(tTIO *board, Boolean tio1)
    {
    unsigned int ClCoRe ;    // clock configuration register value
    if (tio1) board_6624a_TIOa->setAddressOffset(0x0800) ;

    // RESET
    // G01 Joint Reset Register (G01ReRe) Address Offset 0x090
    // To reset G0, G1 (reset bit gets cleared automatically)
    // for TIO(0): G01ReRe = 0x000C, to reset G0 and G1
    // for TIO(1): G01ReRe = 0x000C, to reset G0 and G1
    board->G01_Joint_Reset_Register.writeG0_Reset(1) ;    // CRASHES IN THIS CALL <<<<<<<=====
    board->G01_Joint_Reset_Register.writeG1_Reset(1) ;
    // G23 Joint Reset Register (G23ReRe) Address Offset 0x190
    // To reset G2, G3 (reset bit gets cleared automatically)
    // for TIO(0): G23ReRe = 0x000C, to reset G2 and G3
    // for TIO(1): G23ReRe = 0x000C, to reset G2 and G3
    board->G23_Joint_Reset_Register.writeG2_Reset(1) ;
    board->G23_Joint_Reset_Register.writeG3_Reset(1) ;

The return value of _TIO->getBusSpaceReference() and
_TIO->getAddressOffset(s) appear to be not working right. In walking through
the debugger, the getBusSpaceReference() returns a tBusSpaceReference
structure with both data members set to 0xcdcdcdcd instead of the initial
values generated with the line of code:

  bar1_6624a = bud_6624a->createAddressSpace(kPCI_BAR1);

Any thoughts?
Thanks!
-erik

  and stored inside the bar1_6624a data structure.

[Malcolm]

I've seen that before the device is actually disabled in the OS.  I was running Linux and lspci -vv showed the divice as disabled.  The solution is to go into the BIOS and set PNP OS to False.  That forces the BIOs to enumerate the PCI bus instead of relying on the OS.

A couple of other ideas:

- What OS are you using?

- Have you run one of the MHDDK examples?  Do these fail the first time you write to the TIO as well?

- Try reading the Signature register (tChip_Signature_Register) and see what you read back.  If it's 0xcdcdcdcd then I'm certain that you are not getting a valid bus object.