Is a single channel rate of 500 kS/s really the maximum for AO-DMA using the DDK?
I read this 9 year old post in the forum:
That one suggests to set a value of 0x600 to a non-documented MITE register at offest 0x28, in order to enable DMA burst operation. I found also the related additon to the Comedi MITE implementation, which got a little bit more details:
Does this apply to the PCI-6251 as well, or am I looking at the wrong place?
My implementation used examples/aoex5.cpp as a template. I found that offset 0x28 is covered in the DDK by the MITE BaseAddress class, and so I added mite1->BaseAddress.setValue(0x600); right after configuring the DMA and clearing and resetting the FIFO. This didn't have any apparent effect, though, and perhaps this is a different offset that is 0x28 only by coincident.
Any ideas how to bring the AO-HW-DMA sample rate above 1 MS/s would be welcome.
Solved! Go to Solution.
I guess I found a solution. I switched the AO DMA operation to 32bit, and now it is working at the full sample rate of 2.86 MHz (update divisor = 7).
The obscure burst bits (0x600) at address 0x28 don't make any difference for me, and I don't follow this anymore.
Anyway, I got what I need.