running fpga vi from host vi issues

[incisive]

Hi..
I am using flexrio system with fpga 7962R and adaptor module 6587.
I am trying to run the host vi for data generation from a file on host for my test board.

The problem is when I run the generation host vi with embedded fpga vi( checking run fpga vi, dynamic run), it does not work on first attempt. each time i have to run the fpga vi along with host vi. then stop both of them and run the host vi which results in the flow of data to the dma fifo on fpga vi. why is it so? how can I make the fpga vi tun in one go from the host vi?
Note: My other acquisition program is working fine. The problem is with data generation.

[johnr4]

Hello incisive,

It sounds like your host VI depends on the FPGA (target) VI, or vice versa (depending on the order in which you are running them).  Could you provide more information on what you are doing in both VIs (screenshots would be great)?  Also, do you see an error when trying to run the host without the target running or does it just not work properly?  If you are comfortable posting your code, I could take a look at it as well.

Thanks,

John

NI

[incisive]

in generation vi, i am reading data from tdms file in the host vi, transfering data through dma fifo from host to fpga vi..and that data should then be available on fpga ports.
In data aquisition vi, i am aquiring external data on lvds ports, then transfering data from fpga to host vi through dma fifo and write it in tdms file.
no i don't get any error. The host vi runs smoothly..i can even see the data changing on indicators but don't get anything on the port. when I run fpgs vi once, then it starts to yransfer data to the port.

[Jacobson-ni]

Could you attach the project you are running which demonstrates this behavior? If you are confident that you are not receiving any errors then it's probably something with the FPGA or host initialization that isn't quite right.

[incisive]

I have initialized the host and FPGA VIs as in the example, Finite data generation and acquisition.

The host has Adaptor module iniitalized first and then the FPGA run enabled. 

In FPGA the data direction port set first along with clock out enable signals set in the first sequence. then delay of 500ns for adaptor modue lvds buffer initialization as explained in the example. then the single cycle timed loop enabled in the last sequence structure.

I don't understand what am I doing wrong. 

[Jacobson-ni]

It's very difficult to know if something is wrong by you describing the VI. If you could attach your project we would have a better chance of figuring this out. My gut reaction is the same as John's but, again, it's hard to be certain without seeing what you are doing.

[incisive]

These are the VIs I am using for Data generation. Everytime I have to run the host vi then fpga vi and then the host vi to get data on ports. I have enabled run Dynamic VI option in  open FPGA VI reference. 

Please see what am I doing wrong.

[AgentAstronaut]

Hi incisive,

I took a look at your code and I'm not exactly certain what is going wrong, but I see some pain places that could be causing the problem. Let me ask a question first.

It seems like your run order is:

1. Run Host

2. Run FPGA

3. Run Host

For short hand I will call this the "Start Process".

When and how does the host stop in order to run it again? In what circustance do you need to go through the Start Process again? Is it when you restart the chassis, close LabVIEW, or something else?

The first area of concern is that you don't write to the LVDS_Data_Dir until the FPGA is well past reading that value. You should edit the following part of this code so that it only moves past the while loop when you initialize the values.

The next area of concern is that you are using a bitfile. Make sure your bitfile is up to date with your current code.

Finally, the TDMS portion seems like it is reading from code seperate from the actual generation. This leads me to ask, how are you confirming that data is on your "ports"?

Cheers,

Michael

[incisive]

Hi,

Thanks for the reply.

You are right. This is the start process andcI have to do it every time I run the Host VI for the first time. Even if i switch to some other program or shut down the PC then rerun it ..simple every first time needs it.

Your opinion of making sure that FPGA has read the values, how do I make sure?What changes do I need to make on this part? This is sequential programming.. Do I need to change the stop button of while loop to control? Or do I add one more sequence for data direction?

I am visualizing the pattern generated from the tdms file on the oscilloscope. I see a data pattern after the FPGA VI runs. so I conclude there is no data on ports. by ports I mean the interface card NI SMA 2164.