Hello,
I am attempting to use the NI HSDIO-6652 sample clock (on-board clock is clock source) exported via DDC CLK OUT to act as the clk_in for a simple logic circuit on an external DUT. The logic on the DUT is a long shift register which shifts data at the rising edge of it's clk_in input. The issue I am having is that when niHSDIO Write Named Waveform.vi executes the sample clock enables before the labview code has even executed the NiHSDIO Initiate vi (this was observed on oscillosope). Since the shift clock for the DUT is the sample clock I end up losing data in the shift registers. I need to be able to shift in a data for exactly X clock cycles.
Is there a better way I could be doing this or is there a way to export the sample clock only while the active data event is occurring? Or is there a way to have the start trigger follow the sample clock?
Thanks,
Scott
