hsdio 6556 loses lock on external clock

[Mar1]

Hi,

I am encountring a strange problem. I am using my HSDIO 6556 to generate some pattern using and external clock (around 20MHz, and 50ohm impedance). This clock is provided by an MCU and the whole application is working well. However, when I tried to cool the MCU (down to -10°) the HSDIO loses the lock and attempts to re-lock again (the active led turned red). When this happens, I can see in the scope a new phase shift between the generated data and the external clock, which is fatal for my application. From the otherside I inspected the generated data looking for some glitch or jitter appearing at low temperature... Nothing special noticed..I tried to heat the MCU up to 100°, HSDIO does not lose lock...

What can I do? HSDIO 6556 is seemingly too sensitive...

Mar1

[Jesse_O]

Hello Mar1,

When you cool the MCU are you also cooling the PXIe-6556?  What is happening to the MCU output clock as you cool it?  How much does the frequency/phase change from the original clock?

You mention that you are using a 20MHz reference clock.  What sample clock rate are you running the PXIe-6556 at?

[Mar1]

I am cooling locally the MCU, HSDIO is far away. The external clock generated from the MCU is delivred by an internal PLL. Certainly this PLL  is a little bit sensetive to the temperature, but not to a way that will lead to HSDIO failure. Otherwise I will certainly see an anomaly on the scope. The only thing that occurs to the signal is that the rise/fall time are becomming faster (which is expected), there is no additionnal jitter nor glitches...

This square waveform is used as a sampling clock clock not a reference clock. But to my understanding, HSDIO has to lock on this signal. When it locks for the first time, I can observe a phase shift which is random (within one or 1/2 clock cycle window, I forgot) but this shift will be conserved as long as Im still feeding the HSDIO CLK IN. If I reset my MCU ,I create discontinuty on the clock, and HSDIO re locks again but on different random phase **bleep**. What it happens when I cool the MCU is that HSDIO re locks randomly eventhough I dont reset the MCU. This behaviour can be seen also if there is a great jitter in the clock...

[Jesse_O]

Hello Mar1,

The PXIe-6556 has a fairly large lock and track range.  The lock range is how far off the reference clock can be from what you've provided to the HSDIO driver.  For example if you have a 20MHz clock with 100ppm accuracy, the lock range required would be 100ppm.  The track range is how much the clock will drift in frequency with time/temp.  So if the clock locks at 20MHz, then drifts 100ppm, the drift range required would be 100ppm. 

The actual lock and track range will vary slightly based on the reference clock frequency and the desired output frequency but even the smallest track range should be fairly large.  If you can provide both I might be able to provide more information.  Slightly changing the output frequency (in the Hz range) might make a difference. 

[Mar1]

Hi Jesse,

After more inverstigation, I noticed some 200ps jitter(p-p) added to my signal after cooling. At ambiant temperature it was just 600ps, then it turned to 800ps. I did this by making eye pattern jitter measurement on scope. I also activated the persistance feature and I observed the jitter becomming larger... Now that we have the root cause, what can I do to keep my application working even at low tempertures??

[Brian-G]

Hello Mar1,

Are you importing the external sample clock through CLK IN or PFI 5 (STROBE)? Can you try importing the sample clock through PFI 5 (STROBE) and set the frequency to <20 MHz in software to allow the clock to bypass the PLL circuitry? 

[Kyle_A.]

Hello,

I think Brian's suggestion to attempt bypassing the PLL is to actually use that clock as the source for generation on the 6556 rather than the reference.  However, note that STROBE is for acquisition only, and the way you'd want to bypass the PLL is by setting the CLK IN as the sample clock in your code instead of reference clock.  Mar1, are you sampling at 20 MHz with the generation, or at a faster rate?

[Mar1]

Hi,

As mentionned by Kyle, I cant use the STROBE signal because I am in generation mode. I am using frequencies going from 20Mhz to 90Mhz . I would like to remind you that I do know that my IC has some jitter, and I've tested 6556 with some other ICs that have reduced jitter, I it worked fine. All I want to know is the "Jitter" limit above which the PLL losses the lock. I am aware that in "sampling clock" or "reference clock" modes, there is a  PLL in the loop that I can not bypass and that I have to meet its jitter/voltage/frequency specification.

Rgrds

[Brian-G · Accepted solution]

Hi Mar1,

The public datasheet for the clocking chip used in the PXIe-6556 states a jitter tolerance of 20,000 ppm typical, with 5000 ppm minimum. For a 20 MHz clock, this would correspond to 1 ns of jitter typical, and 250 ps in the worst case. That being said, we cannot guarantee any specification that is not included in the NI PXIe-6555/6556 Specifications document because it is not production tested.

Best regards,

[Mar1]

Hi,

This is the information I looked for. Thanks a lot.

Best regards.

Mar1