06-18-2014 06:57 AM
Hi
I have four PCIe6535s and synchronizing them with "sample clock" and "start trigger" exported via RTSI line 7 and 1 respectivelly from one of the boards, operating in Master(4) Slave(1-3) configuration with the last board sending the clock and trigger.
The trigger will trigger 3-5 times on all boards and then only the master card will trigger and others will not trigger.
I have also seen when one or two will trigger and the rest will not.
Since the master always triggers it cannot be the quality of the triggering signal, but something at the RTSI level.
Where can I look and where to poke around?
thanks
Solved! Go to Solution.
06-20-2014 04:28 AM - edited 06-20-2014 04:58 AM
I enclosed the screendump from the scope monitoring DIO0&1 from all four boards.
As you can see the boards started but never finished the task. They reported error on time out.
It seems they go into some sort of high impedance mode as indicated by a small nips when the trigger changes (induced).
There is no rule which board is finishing or not. Even the board which exports the trigger signal may not finish the task while the other will.
Any ideas?
06-20-2014 05:54 AM
I have also found that hen the error happens the tasks which failed did not write all the samples to the board ("TotalSamplPerChanGenerated" returns N-1 samples written. So the last sample has never made it to the board.
06-20-2014 08:32 AM
OK, found the problem.
Since the last board was outputing the sample clock, the three slave boards from time to time did not manage to output the full buffer (one sample short).
Now the solution is to configure the slave's clock to use one less sample to output the data. The buffer will be one sample short, but at least all the tasks are finished.
It would be nice however, if the error indicated that the buffer and the sample clock have mismatch, would save me a day.