PXIe support with respest to digital I/O

[sunnykillz]

Hi, I have developed a program for demodulation of RF data stream in FPGA 7999 interfaced with NI tranceiver 5791.Data gets demodulated and than stored to FIFO as required. After acquiring RF data stream it gets demodulated IN FPGA.Recovered data is than output from NI 5791 transceiver Digital IO port. I have question regarding data which is getting out from 5791 is in pulse like form.BUt I require data to be of continuous type rather than pulse form. My second query is that I also want to generate clock with the demodulated data.Right now I have mapped output enable pulse at output but my objective is to output a proper clock with akllmost 50% duty cycle with continuos demodulated data. VI is attached kindly look and guide accordingly.Thanks sample project is also attached

[sunnykillz]

Host VI is attached now previous was FPGA VI

[sunnykillz]

Host VI is attached

[sunnykillz]

host vi

[sunnykillz]

please reply I am stuck in end of my project

[sunnykillz]

Please see jpg to further clarify my issue

[sunnykillz]

jpg

[sunnykillz]

Dont know why attachment is not being uploaded

[Kaleb_A]

Hello sunnykillz,

What NI FlexRIO product are you using? I'm not showing the 7999 as a National Instruments FlexRIO device.

What PXIe chassis and PXIe controller are you using?

Your demodulated signal (recovered data) is a continuous Analog signal correct? You won't be able to output an Analog signal from a Digital I/O port. The Digital I/O port is only capable of 3.3 LVCMOS logic (which basically means a ~3.3 V High pulse or ~0 V Low pulse).

Are you wanting to transmit out (TX OUT) the time domain signal that you demodulated?

For outputting a clock, you can use the front panel terminal CLK OUT to export a clock signal. The NI-579x Configuration Design Library allows you to program your clock sources. Please see page 21 of the 5791R User Manual for information on available clock sources.

Please try to post your .png again!

Best regards,

[sunnykillz]

Hello Anderson, PXIe chassis number is NI PXIe- 1085 with PXIe controller PXIe-8135. My demodulated (recovered bits) are stored on FIFO and that means they are in digital format.These FIFO bits I read in HOST VI which are correct and are same as they were before modulation. I you see my FPGA VI you will understand that easily.Now I was trying to get this Stored recovered data to be outputted on PFI lines of NI tranceiver 5791.Data gets out from PFI line but its format is not continuous type rather it is pulse like.This can be observed in JPG attached. With data I also want to output synced clock out from PFI lines too. Let say data is demodulated at 512kbps so a clock of 512KHz and data synced with this clock should be outputted from PFI lines. This is being done to complete a loop back test via ROHDE & SCHWARZ SMJ100. Best Regards Muhammad Rizwan